Patents by Inventor Yoshihisa Imori
Yoshihisa Imori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11264313Abstract: A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.Type: GrantFiled: February 1, 2019Date of Patent: March 1, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Akito Shimizu, Yasuhisa Shintoku, Yoshihisa Imori, Hiroaki Kishi, Atsushi Hosokawa, Tomohiko Imada, Shinya Shimamura
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Patent number: 10840166Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.Type: GrantFiled: September 12, 2018Date of Patent: November 17, 2020Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Kumiko Karouji, Morihiko Ikemizu, Yoshihisa Imori, Hiroaki Kishi, Tomohiko Imada, Akito Shimizu
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Patent number: 10790219Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.Type: GrantFiled: May 20, 2019Date of Patent: September 29, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Imori, Kenji Yamada
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Publication number: 20200083150Abstract: A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.Type: ApplicationFiled: February 1, 2019Publication date: March 12, 2020Inventors: Akito Shimizu, Yasuhisa Shintoku, Yoshihisa Imori, Hiroaki Kishi, Atsushi Hosokawa, Tomohiko Imada, Shinya Shimamura
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Publication number: 20190295923Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.Type: ApplicationFiled: September 12, 2018Publication date: September 26, 2019Inventors: Kumiko Karouji, Morihiko Ikemizu, Yoshihisa Imori, Hiroaki Kishi, Tomohiko Imada, Akito Shimizu
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Publication number: 20190273035Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Inventors: Yoshihisa Imori, Kenji Yamada
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Patent number: 10340207Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.Type: GrantFiled: September 11, 2017Date of Patent: July 2, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Imori, Kenji Yamada
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Publication number: 20180247883Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.Type: ApplicationFiled: September 11, 2017Publication date: August 30, 2018Inventors: Yoshihisa Imori, Kenji Yamada
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Patent number: 9887311Abstract: A semiconductor module includes a light emitting element, a semiconductor element including a light receptor circuit disposed to receive light from the light emitting element, a light-transmissive insulating body disposed between the light emitting element and the semiconductor element, at least one of a first surface thereof facing the semiconductor element and a second surface thereof facing the light emitting element including a ragged region, a first light-transmissive bonding resin formed between the light emitting element and the light-transmissive insulating body, and a second light-transmissive bonding resin formed between the semiconductor element and the light-transmissive insulating body.Type: GrantFiled: August 30, 2016Date of Patent: February 6, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kurosawa, Yoshihisa Imori
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Publication number: 20170244003Abstract: A semiconductor module includes a light emitting element, a semiconductor element including a light receptor circuit disposed to receive light from the light emitting element, a light-transmissive insulating body disposed between the light emitting element and the semiconductor element, at least one of a first surface thereof facing the semiconductor element and a second surface thereof facing the light emitting element including a ragged region, a first light-transmissive bonding resin formed between the light emitting element and the light-transmissive insulating body, and a second light-transmissive bonding resin formed between the semiconductor element and the light-transmissive insulating body.Type: ApplicationFiled: August 30, 2016Publication date: August 24, 2017Inventors: Tetsuya KUROSAWA, Yoshihisa IMORI
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Patent number: 8338904Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.Type: GrantFiled: September 16, 2010Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
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Patent number: 8084499Abstract: Modified clay minerals obtained by treating a clay mineral with a particular acylarginine derivative are useful for stabilizing emulsion compositions, inter alia, W/O emulsion composition, while hardly causing skin irritation, and providing moisture retention properties.Type: GrantFiled: September 30, 2008Date of Patent: December 27, 2011Assignee: Ajinomoto Co., Inc.Inventors: Souichirou Ootake, Yoshihisa Imori, Tetsuya Izumi
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Publication number: 20110073983Abstract: According to an embodiment, there is provided a semiconductor device including a semiconductor substrate having a first surface on which an active layer having a light receiving portion is provided and a second surface to be a light receiving surface for the light receiving portion, a wiring layer provided on the active layer, an insulating layer provided to cover the wiring layer, and a supporting substrate joined to the semiconductor substrate via the insulating layer to face the first surface of the semiconductor substrate. A joined body of the semiconductor substrate and the supporting substrate includes an intercalated portion provided between its outer peripheral surface and the active surface. The intercalated portion is provided to penetrate the semiconductor substrate and the insulating layer from the second surface of the semiconductor substrate and to reach inside the supporting substrate.Type: ApplicationFiled: September 16, 2010Publication date: March 31, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumasa Tanida, Chiaki Takubo, Hideo Numata, Yoshihisa Imori
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Patent number: 7880301Abstract: A semiconductor device includes a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and including a low dielectric constant insulating film, and a laser-machined groove provided to cut at least the low dielectric constant insulating film. The semiconductor element is connected to a wiring substrate via a bump electrode. An underfill material is filled between the semiconductor element and the wiring substrate. The fillet length Y (mm) of the underfill material satisfies a condition of Y>?0.233X+3.5 (where X>0, and Y>0) with respect to the width X (?m) of the laser-machined groove.Type: GrantFiled: September 20, 2007Date of Patent: February 1, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihisa Imori
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Patent number: 7638858Abstract: A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a curved surface provided at an intersection of a side surface of the notch and the rear surface of the substrate.Type: GrantFiled: April 5, 2007Date of Patent: December 29, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kurosawa, Yoshihisa Imori
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Patent number: 7608911Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: June 24, 2008Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Publication number: 20090098169Abstract: Modified clay minerals obtained by treating a clay mineral with a particular acylarginine derivative are useful for stabilizing emulsion compositions, inter alia, W/O emulsion composition, while hardly causing skin irritation, and providing moisture retention properties.Type: ApplicationFiled: September 30, 2008Publication date: April 16, 2009Applicant: AJINOMOTO CO., INCInventors: Souichirou Ootake, Yoshihisa Imori, Tetsuya Izumi
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Publication number: 20080265443Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: ApplicationFiled: June 24, 2008Publication date: October 30, 2008Applicant: Kabushiki Kaisha Toshiba,Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 7405159Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: March 1, 2007Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Publication number: 20080073780Abstract: A semiconductor device includes a semiconductor element including a semiconductor substrate having an element region, a laminated film formed on the semiconductor substrate and including a low dielectric constant insulating film, and a laser-machined groove provided to cut at least the low dielectric constant insulating film. The semiconductor element is connected to a wiring substrate via a bump electrode. An underfill material is filled between the semiconductor element and the wiring substrate. The fillet length Y (mm) of the underfill material satisfies a condition of Y>?0.233X+3.5 (where X>0, and Y>0) with respect to the width X (?m) of the laser-machined groove.Type: ApplicationFiled: September 20, 2007Publication date: March 27, 2008Inventor: Yoshihisa Imori