Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.

Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.

Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.

Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.

Abstract: According to one embodiment, an image processor is disclosed. The image processor can include a material image drawing portion drawing a material image, the material image is a material for a 3D display, a material image memory portion storing data of the material image drawn by the material image drawing portion, and an image generator generating image data for the 3D display on a basis of the data of the material image read from the material image memory portion, depth information configured to the material image, and viewpoint position information preliminary configured, and outputting the image data to a display portion.