Abstract: A one-chip IC device has a plurality of IC-chip equivalent regions which have substantially the same patterns and functions as those of ICs whose functions are already evaluated and proven. The device has intra-region wiring layers in the IC-chip equivalent regions. The device also has external lead contacts which have been used as bonding pads of the original ICs, in addition to outer bonding pads. Second wiring layers are connected between the external lead contacts and between the external lead contacts and the outer bonding pads.

Abstract: A CMOS device has P- and N-channel transistors sandwiching an isolation region formed on a semiconductor substrate. The drain regions, as well as the gate regions, of both transistors are connected by respective wiring layers made of polycrystalline silicon. Electrical contacts between the drain-connecting polycrystalline silicon wiring layer and each of the drain regions have a symmetrical structure in both transistors. In the electrical contacts, impurity diffusion regions having the same conductivity type as the drain regions and being contiguous with the drain regions are formed on the semiconductor substrate and the well region under the polycrystalline silicon wiring layer. Contact holes are formed in the insulating layer on the impurity diffusion region and on the drain region, and a conductive layer lies within the contact holes to connect the impurity diffusion regions to the polycrystalline silicon wiring layer.

Abstract: A method of manufacturing a mask type read only memory having an interconnection wiring and a plurality of MOS transistors, wherein selected source and drain regions are shortened in accordance with a user program after the interconnection wiring layer is formed on the semiconductor substrate. After that, a protective film is formed over the entire surface of the read only memory.

Abstract: A voltage comparator comprises a first pair of series-connected CMOS transistors and a second pair of series-connected CMOS transistors which are respectively connected in parallel between power supply terminals and clocked by a common clock pulse. A first MOS transistor having its gate supplied with a reference voltage is connected between the first paired CMOS transistors. A second MOS transistor having its gate supplied with an input voltage to be compared with the reference voltage is connected between the second paired CMOS transistors. An RS flip-flop circuit is provided which has a pair of inputs connected to the drains of the first and second MOS transistors, respectively.

Abstract: An integrated circuit having a multi-layer interconnection structure comprises a logic section of series-connected MOS FETs each having a gate input connection layer made of a polysilicon layer on a semiconductor substrate of one conductivity type and source and drain semiconductor regions of the other conductivity type formed in the surface of the substrate along such a direction as to traverse the gate input connection layer, a load device connected to one end of the logic section, and interconnection structure for causing a signal, at a junction of the load device and logic the section, to be transmitted to the other end of the logic section across the gate input connection layer.

Abstract: A matrix circuit acting as a read only memory (ROM) comprises first and second groups of input lines, a third group of input lines arranged between the first and second groups of input lines, a plurality of groups of output lines intersecting the input lines off the first, second and third group, each group of the output lines having one terminal commonly connected in a wired OR fasion to one end of a power source and having the other terminal commonly connected to the ground.