Patents by Inventor Yoshihisa Tange
Yoshihisa Tange has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8702891Abstract: The invention provides a method and an apparatus for manufacturing a glass-sealed package, whereby anodic bonding of a pair of wafers is ensured over substantially the whole area of the wafers, and whereby a vacuum is ensured inside the cavity during the anodic bonding of the wafers. The invention also provides an oscillator having such characteristics. The manufacturing method of a glass-sealed package includes the step of anodically bonding a pair of wafers by applying voltage to positions corresponding to circumferential portions of the wafers stacked in layers, and the step of dividing the pair of anodically bonded wafers into individual pieces. A through hole is formed at a central portion of at least one of the wafers, and the anodic bonding of the wafers is made by applying voltage using a plurality of electrodes disposed at the positions corresponding to the circumferential portions of the wafers.Type: GrantFiled: February 5, 2010Date of Patent: April 22, 2014Assignee: Seiko Instruments Inc.Inventor: Yoshihisa Tange
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Patent number: 8656740Abstract: The invention provides a manufacturing method of a glass-sealed package, and a glass substrate used for the glass-sealed package, whereby an amount of warp in a glass substrate is reduced to improve processing accuracy in a subsequent step in which the glass substrate is combined (such as by anodic bonding) with another glass substrate provided with a thin film. The front side of the glass substrate includes a region where the cavities used to house electronic devices such as semiconductor IC chips and crystal blanks are not formed. The region devoid of the cavities is provided in the formed of a frame to reduce an amount of warp in the glass substrate.Type: GrantFiled: February 19, 2010Date of Patent: February 25, 2014Assignee: Seiko Instruments Inc.Inventor: Yoshihisa Tange
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Patent number: 8448312Abstract: A method of manufacturing packages includes a welding step for welding a base substrate wafer to a rivet member by heating the base substrate wafer while pressing the same by a forming die from both sides in the thickness direction is provided, wherein a rivet member receiving portion which can receive a distal end of a core member is formed in a receiving die of the forming die, and an inner surface of the rivet member receiving portion is formed into a tapered shape widening from the bottom side toward the opening side.Type: GrantFiled: July 14, 2011Date of Patent: May 28, 2013Assignee: Seiko Instruments Inc.Inventor: Yoshihisa Tange
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Patent number: 8405359Abstract: Provided are a battery protection IC adaptable to any number of batteries connected in series without increasing a breakdown voltage thereof, and a battery device including the battery protection IC mounted thereon. A charge control signal input terminal and a discharge control signal input terminal of one battery protection IC are provided with a clamp circuit (121), and hence an output driver (112) of another battery protection IC connected to those terminals is not applied with a voltage equal to or higher than a breakdown voltage. Accordingly, the breakdown voltage of the battery protection IC is not required to be high.Type: GrantFiled: July 3, 2008Date of Patent: March 26, 2013Assignee: Seiko Instruments Inc.Inventors: Yoshihisa Tange, Atsushi Sakurai, Takakazu Ozawa, Kiyoshi Yoshikawa
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Patent number: 8179099Abstract: Provided is a battery state monitoring circuit including a control circuit that applies, to a gate of a signal output transistor provided at a terminal for transmitting an overcharge detection signal, a potential at which the signal output transistor is turned off at a voltage lower than a minimum circuit operating voltage. Accordingly, in a battery device that uses the cascade-connected battery state monitoring circuits, charge is inhibited securely even at a power supply voltage lower than the minimum circuit operating voltage.Type: GrantFiled: October 20, 2009Date of Patent: May 15, 2012Assignee: Seiko Instruments Inc.Inventor: Yoshihisa Tange
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Publication number: 20120013415Abstract: A method of manufacturing packages includes a welding step for welding a base substrate wafer to a rivet member by heating the base substrate wafer while pressing the same by a forming die from both sides in the thickness direction is provided, wherein a rivet member receiving portion which can receive a distal end of a core member is formed in a receiving die of the forming die, and an inner surface of the rivet member receiving portion is formed into a tapered shape widening from the bottom side toward the opening side.Type: ApplicationFiled: July 14, 2011Publication date: January 19, 2012Inventor: Yoshihisa TANGE
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Patent number: 8058845Abstract: Provided is a battery state monitoring circuit which is capable of preventing a discharge leak current from a battery so as to eliminate a load conventionally imposed on a user, including: a battery state detector circuit that detects a state of the battery based on a voltage of the battery; a transmitting terminal that transmits battery state information indicative of the state of the battery to an outside; a receiving terminal that receives battery state information of another battery from the outside; a transistor that is used for transmitting the battery state information, and has any one of two terminals except for a control terminal connected to the transmitting terminal; and a diode that is connected in a direction opposite to a direction of a parasitic diode disposed between the two terminals of the transistor, the diode being disposed between the transmitting terminal and one terminal of the transistor.Type: GrantFiled: July 3, 2008Date of Patent: November 15, 2011Assignee: Seiko Instruments Inc.Inventors: Yoshihisa Tange, Atsushi Sakurai, Takakazu Ozawa, Kiyoshi Yoshikawa
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Publication number: 20110193645Abstract: In a piezoelectric vibrator in which a piezoelectric vibrating reed is mounted on a mounting portion installed on a surface of the base substrate in a cantilevered state and the piezoelectric vibrating reed is accommodated to be covered by a lid substrate, the resistance of a lead-out electrode for supplying a drive power to the piezoelectric vibrating reed is reduced, thereby preventing degradation of vibrating performance. A first lead-out electrode formed between a mounting portion of a base substrate and a first through-electrode is formed in a peripheral region so as not to overlap with first and second excitation electrodes formed on outer surfaces of a piezoelectric vibrating reed for driving, thereby reducing the resistance of the first lead-out electrode.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Inventor: Yoshihisa Tange
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Publication number: 20110193642Abstract: In a piezoelectric vibrator in which a piezoelectric vibrating reed is mounted on a mounting portion installed on a surface of the base substrate in a cantilevered state and the piezoelectric vibrating reed is accommodated to be covered by a lid substrate, the resistance of a lead-out electrode for supplying a drive power to the piezoelectric vibrating reed is reduced, thereby preventing degradation of vibrating performance. A first lead-out electrode is formed between a first through-electrode and a mounting portion formed on a base substrate, a conductor film is formed from a bonding member on a bonding surface where the base substrate and a lid substrate are bonded to each other, the first lead-out electrode and the conductor film are electrically connected to each other via the first connection portion in the vicinity of the mounting portion and via the second connection portion in the vicinity of the first through-electrode, thereby reducing the resistance of the first lead-out electrode.Type: ApplicationFiled: February 3, 2011Publication date: August 11, 2011Inventors: Yoshihisa Tange, Yoshifumi Yoshida
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Publication number: 20110193643Abstract: Provided is a method of manufacturing a package capable of providing a plurality of through-electrodes in a base substrate made of a glass material with high position precision. An electrode member having a plurality of pins erected on a base is prepared, the plurality of pins is inserted into a plurality of through-holes of a glass substrate provided with the plurality of through-holes, the resultant is heated to a temperature higher than the softening point of the glass substrate to weld the corresponding through-holes and the pins to each other, the glass substrate is ground after cooling to remove the base, and the pins are exposed from both surfaces of the glass substrate, thereby forming through-electrodes which are electrically separated from each other.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Inventors: Yoshihisa Tange, Yoshifumi Yoshida
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Publication number: 20110193644Abstract: In a piezoelectric vibrator in which a piezoelectric vibrating reed is mounted on a mounting portion installed on a surface of the base substrate in a cantilevered state and the piezoelectric vibrating reed is accommodated to be covered by a lid substrate, the resistance of a lead-out electrode for supplying a drive power to the piezoelectric vibrating reed is reduced, thereby preventing degradation of vibrating performance. A first lead-out electrode is formed between a first through-electrode and a mounting portion formed on a base substrate, a second lead-out electrode is formed on a surface of a lid substrate on the base substrate side, the first and second lead-out electrodes are electrically connected to the first and second connection portions in the vicinities of the mounting portion and the first through-electrode, respectively, thereby reducing the resistance of the lead-out electrode.Type: ApplicationFiled: February 4, 2011Publication date: August 11, 2011Inventor: Yoshihisa Tange
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Patent number: 7990669Abstract: Provided is a battery protection circuit and a battery device which may be manufactured at lower cost. Before all terminals of a battery protection circuit are each connected to batteries, even when a logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by P-wells due to a connection order in which the batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the P-wells. For this reason, a charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order.Type: GrantFiled: February 26, 2009Date of Patent: August 2, 2011Assignee: Seiko Instruments Inc.Inventors: Kiyoshi Yoshikawa, Atsushi Sakurai, Toshiyuki Koike, Kazuaki Sano, Yoshihisa Tange
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Publication number: 20110140571Abstract: There is provided a package manufacturing method capable of manufacturing high-quality and high-accuracy products without requiring complicated processes. A method for manufacturing a package including a base board and a lid board bonded to each other so as to form a cavity at an inner side and penetration electrodes that electrically connect the inside of the cavity to the outside of a base board made of a glass material includes a penetration hole forming step of forming penetration holes in a base board wafer; a rivet member insertion step of inserting conductive rivet members made of a metal material into the penetration holes; a welding step of heating the base board wafer to a temperature higher than the softening point of the glass material so as to weld the base board wafer to the rivet members; and a cooling step of cooling the base board wafer.Type: ApplicationFiled: December 8, 2010Publication date: June 16, 2011Inventors: Yoshihisa Tange, Yoshifumi Yoshida
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Patent number: 7923968Abstract: A charge and discharge control circuit which accommodates pulsed charge and pulsed discharge and can control charge and discharge of a secondary battery with safety, and a rechargeable power supply device having the same built therein are provided. The charge and discharge control circuit includes a delay time switching circuit for shortening a delay time of overcharge detection after charge inhibition is canceled. When overcharge is detected after the charge inhibition is canceled, the charge is inhibited in a delay time which is shorter than a normal delay time of the overcharge detection.Type: GrantFiled: August 28, 2008Date of Patent: April 12, 2011Assignee: Seiko Instruments Inc.Inventors: Kazuaki Sano, Kiyoshi Yoshikawa, Toshiyuki Koike, Yoshihisa Tange, Atsushi Sakurai
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Publication number: 20100215906Abstract: The invention provides a manufacturing method of a glass-sealed package, and a glass substrate used for the glass-sealed package, whereby an amount of warp in a glass substrate is reduced to improve processing accuracy in a subsequent step in which the glass substrate is combined (such as by anodic bonding) with another glass substrate provided with a thin film. The front side of the glass substrate includes a region where the cavities used to house electronic devices such as semiconductor IC chips and crystal blanks are not formed. The region devoid of the cavities is provided in the formed of a frame to reduce an amount of warp in the glass substrate.Type: ApplicationFiled: February 19, 2010Publication date: August 26, 2010Inventor: Yoshihisa Tange
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Publication number: 20100207698Abstract: The invention provides a method and an apparatus for manufacturing a glass-sealed package, whereby anodic bonding of a pair of wafers is ensured over substantially the whole area of the wafers, and whereby a vacuum is ensured inside the cavity during the anodic bonding of the wafers. The invention also provides an oscillator having such characteristics. The manufacturing method of a glass-sealed package includes the step of anodically bonding a pair of wafers by applying voltage to positions corresponding to circumferential portions of the wafers stacked in layers, and the step of dividing the pair of anodically bonded wafers into individual pieces. A through hole is formed at a central portion of at least one of the wafers, and the anodic bonding of the wafers is made by applying voltage using a plurality of electrodes disposed at the positions corresponding to the circumferential portions of the wafers.Type: ApplicationFiled: February 5, 2010Publication date: August 19, 2010Inventor: Yoshihisa Tange
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Publication number: 20100097033Abstract: Provided is a battery state monitoring circuit including a control circuit that applies, to a gate of a signal output transistor provided at a terminal for transmitting an overcharge detection signal, a potential at which the signal output transistor is turned off at a voltage lower than a minimum circuit operating voltage. Accordingly, in a battery device that uses the cascade-connected battery state monitoring circuits, charge is inhibited securely even at a power supply voltage lower than the minimum circuit operating voltage.Type: ApplicationFiled: October 20, 2009Publication date: April 22, 2010Inventor: Yoshihisa Tange
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Publication number: 20100060084Abstract: Provided are a battery protection IC adaptable to any number of batteries connected in series without increasing a breakdown voltage thereof, and a battery device including the battery protection IC mounted thereon. A charge control signal input terminal and a discharge control signal input terminal of one battery protection IC are provided with a clamp circuit (121), and hence an output driver (112) of another battery protection IC connected to those terminals is not applied with a voltage equal to or higher than a breakdown voltage. Accordingly, the breakdown voltage of the battery protection IC is not required to be high.Type: ApplicationFiled: July 3, 2008Publication date: March 11, 2010Applicant: Seiko Instruments Inc.Inventors: Yoshihisa Tange, Atsushi Sakurai, Takakazu Ozawa, Kiyoshi Yoshikawa
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Publication number: 20090243543Abstract: Provided is a charge and discharge control circuit capable of further preventing poor charge of a battery, and a battery device. Cell balance periods are detected before charge of respective batteries is stopped even when an overcharge detection voltage of a certain charge and discharge control circuit becomes lower than a cell balance period detection voltage thereof due to process variations occurring in mass production of the charge and discharge control circuits. That is, the charge of the respective batteries is stopped after cell balance control. Therefore, the respective batteries can be further prevented from being poorly charged.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Inventors: Muneharu Kawana, Atsushi Sakurai, Kazuaki Sano, Toshiyuki Koike, Yoshihisa Tange
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Publication number: 20090213511Abstract: Provided is a battery protection circuit and a battery device which may be manufactured at lower cost. Before all terminals of a battery protection circuit are each connected to batteries, even when a logical circuit malfunctions by an operation of a parasitic bipolar transistor formed by P-wells due to a connection order in which the batteries are connected, the logical circuit is reset by an operation of a parasitic bipolar transistor formed by the P-wells. For this reason, a charge/discharge path of the batteries is not interrupted due to the connection order. Accordingly, no limitation is placed on the connection order.Type: ApplicationFiled: February 26, 2009Publication date: August 27, 2009Inventors: Kiyoshi Yoshikawa, Atsushi Sakurai, Toshiyuki Koike, Kazuaki Sano, Yoshihisa Tange