Abstract: According to one embodiment, provided is a display device with an improved manufacturability which is capable of preventing a decrease in the display quality due to a change in the gap between an array substrate and a counter substrate caused by a temperature change. The primary bonding portion is composed of translucent synthetic resin and provided to bond together the counter substrate side and a touch panel side in a manner covering at least a display area. The secondary bonding portion is provided in a columnar shape through curing of adhesive being ultraviolet curable liquid resin with a viscosity higher than that of the synthetic resin of the primary bonding portion, the secondary bonding portion bonding together the non-opposed portion side and the touch panel side.

Abstract: According to one embodiment, provided is a display device with an improved manufacturability which is capable of preventing a decrease in the display quality due to a change in the gap between an array substrate and a counter substrate caused by a temperature change. The primary bonding portion is composed of translucent synthetic resin and provided to bond together the counter substrate side and a touch panel side in a manner covering at least a display area. The secondary bonding portion is provided in a columnar shape through curing of adhesive being ultraviolet curable liquid resin with a viscosity higher than that of the synthetic resin of the primary bonding portion, the secondary bonding portion bonding together the non-opposed portion side and the touch panel side.

Abstract: A belt unit is detachably attached to a housing. A holder changes a state of an endless belt by moving a transfer roller between a first state as an endless belt movement state and a second state as a detachment state. The first state allows the endless belt to circulate for image formation, and the second state allows the belt unit to be detached from the housing. The holder moves the transfer roller adjacent supporter independently of the transfer roller and lifts the opening in the endless belt to a prescribed position to expose it to the front side plate.

Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

Abstract: A lubricant supplying device comprises a solid lubricant, a lubricant applicator to scrape and supply the lubricant to a target, and a pressing mechanism to press the solid lubricant against the lubricant applicator. An amount of pressure applied to the solid lubricant by the pressing mechanism increases until one of a thickness of the solid lubricant and a number of printed sheets reaches a prescribed level after the lubricant starts being consumed.

Abstract: An image forming apparatus includes a receiver to receive image information from an external device, a movable intermediate transfer member, a plurality of latent image bearing members on which a latent image is formed based on the image information, a plurality of developing devices, each of which disposed in proximity to the latent image baring member, to develop the latent image on the latent image bearing member with toner to form a toner image thereon, a transfer bias application mechanism to apply a transfer bias to the intermediate transfer member and halt temporarily and periodically application of the transfer bias in a continuous output mode in which a plurality of images are continuously formed on different recording media sheets based on the image information of the plurality of images received continuously by the receiver, and a secondary transfer member to transfer the superimposed toner image onto a recording medium.

Abstract: A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage level, and a final data write operation of additionally writing final data at the threshold voltage level, includes making at least one of a write time of the preliminary data write operation, a word-line waiting time of verify read, and a bit-line waiting time of verify read, shorter than that of the final data write operation.

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract: A belt unit is detachably attached to a housing. A holder changes a state of an endless belt by moving a transfer roller between a first state as an endless belt movement state and a second state as a detachment state. The first state allows the endless belt to circulate for image formation, and the second state allows the belt unit to be detached from the housing. The holder moves the transfer roller adjacent supporter independently of the transfer roller and lifts the opening in the endless belt to a prescribed position to expose it to the front side plate.

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

Abstract: A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase.

Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

Abstract: A lubricant supplying device comprises a solid lubricant, a lubricant applicator to scrape and supply the lubricant to a target, and a pressing mechanism to press the solid lubricant against the lubricant applicator. An amount of pressure applied to the solid lubricant by the pressing mechanism increases until one of a thickness of the solid lubricant and a number of printed sheets reaches a prescribed level after the lubricant starts being consumed.

Abstract: A panel cell for detecting anti-HNA antibody is disclosed. The panel cell is obtained by introducing a DNA coding for an HNA antigen corresponding to the anti-HNA antibody into a cell so as to enable the expression of the DNA under the condition for use in the detection procedure, wherein the cell for DNA introduction exhibits no detectable reaction with anti-HLA-ABC antibody, anti-HLA-DR antibody, anti-HLA-DQ antibody, anti-HLA-DP antibody, anti-HNA-1 antibody, anti-HNA-2a antibody, anti-HNA-3a antibody, anti-HNA-4 antibody, anti-HNA-5 antibody, and serum from normal subject, in the detection procedure. The panel cell allows accurate and rapid detection of granulocyte antibody.

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections such that the respective sections provide writing voltages for writing different target threshold levels, and brings the bit line connected to the memory cell to be written with any of the target threshold levels into a selected state synchronously to the section for applying the writing voltage for writing that target threshold level.

Abstract: A nonvolatile semiconductor memory includes a memory cell array having a plurality of NAND cell units which are arranged with a plurality of memory cells connected in series and a first selection transistor and a second selection transistor which are each connected to both ends of the plurality of memory cells respectively, a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells and a data read control part wherein at least one of the memory cells is selected and when data is read from that memory cell a read pass voltage is applied to a word line which is connected to a non-selected memory cell other than the selected memory cell, and after applying the read pass voltage a voltage is applied to a control gate of the first selection transistor or the second selection transistor, and when applying the read pass voltage, the read pass voltage which is applied to the word line which is connected to at least one of the non-selected memory cells which is adjacent