Patents by Inventor Yoshihito ICHIKAWA

Yoshihito ICHIKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055258
    Abstract: A manufacturing method of a silicon carbide semiconductor device includes: epitaxially growing a drift layer of a first conductivity-type on a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on the drift layer; forming a main region of the first conductivity-type on the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed; and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after epitaxially growing the drift layer and before forming the gate insulating film.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihito ICHIKAWA, Akimasa KINOSHITA
  • Patent number: 11721756
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 8, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihito Ichikawa, Akimasa Kinoshita, Shingo Hayashi
  • Publication number: 20220285501
    Abstract: At any timing after formation of gate electrodes, particle beam irradiation is performed to a semiconductor wafer having an n?-type drift region constituted by an n?-type epitaxial layer and having an n-type impurity concentration that is higher than a target majority carrier concentration (design value) of the n?-type drift region. Point defects of a defect density corresponding to an irradiation dose of the particle beam are generated in the n?-type drift region by the particle beam irradiation, whereby an effective majority carrier concentration of the n?-type drift region is adjusted and reduced with respect to the n-type impurity concentration of the n?-type drift region, to approach the design value. After formation of the n?-type epitaxial layer, the n-type impurity concentration of the n?-type drift region may be measured, or the n?-type epitaxial layer may be formed to have an n-type impurity concentration higher than the design value.
    Type: Application
    Filed: January 28, 2022
    Publication date: September 8, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihito ICHIKAWA
  • Publication number: 20220069120
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.
    Type: Application
    Filed: June 25, 2021
    Publication date: March 3, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihito ICHIKAWA, Akimasa KINOSHITA, Shingo HAYASHI