Patents by Inventor Yoshihito Kawakami

Yoshihito Kawakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230024780
    Abstract: A switch circuit is configured of a first semiconductor element and a second semiconductor element connected in series, and receives a DC voltage of 100 V or more. The drive circuit causes the first semiconductor element or the second semiconductor element to perform a switching operation. The isolated power supply circuit converts a predetermined power supply voltage into an isolated first power supply voltage, and outputs the first power supply voltage to the drive circuit. The isolation signal converter converts a first signal of 6 MHz or more into an isolated first drive signal, and outputs the first drive signal to the drive circuit. The single substrate mounts the isolated power supply circuit and the isolation signal converter. Both the first semiconductor element and the second semiconductor element are wide bandgap semiconductor elements.
    Type: Application
    Filed: December 17, 2020
    Publication date: January 26, 2023
    Inventors: HIROKI AKASHI, TAKUYA ISHII, YOSHIHITO KAWAKAMI, KAZUHIRO YAHATA, TAKESHI AZUMA, YOSHIHISA MINAMI
  • Patent number: 10848145
    Abstract: A driver circuit which is supplied with a positive power supply voltage, a negative power supply voltage, and an input signal, and drives a switching element including a control terminal according to the input signal includes: a first output terminal connected to the control terminal via a first impedance circuit, and outputs the positive power supply voltage or the negative power supply voltage according to the input signal, to charge the control terminal and put the switching element into an ON state; a negative power supply terminal supplied with the negative power supply voltage; a negative voltage switch having a first end connected to the negative power supply terminal; a third output terminal connected to a second end of the negative voltage switch and to the control terminal via a second impedance circuit; and a first discharge switch disposed between the negative power supply terminal and the first output terminal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 24, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Takuya Ishii, Yoshihito Kawakami, Takahiro Uehara, Ginga Katase
  • Publication number: 20180083610
    Abstract: A driver circuit which is supplied with a positive power supply voltage, a negative power supply voltage, and an input signal, and drives a switching element including a control terminal according to the input signal includes: a first output terminal connected to the control terminal via a first impedance circuit, and outputs the positive power supply voltage or the negative power supply voltage according to the input signal, to charge the control terminal and put the switching element into an ON state; a negative power supply terminal supplied with the negative power supply voltage; a negative voltage switch having a first end connected to the negative power supply terminal; a third output terminal connected to a second end of the negative voltage switch and to the control terminal via a second impedance circuit; and a first discharge switch disposed between the negative power supply terminal and the first output terminal.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 22, 2018
    Inventors: Takuya ISHII, Yoshihito KAWAKAMI, Takahiro UEHARA, Ginga KATASE
  • Publication number: 20150229160
    Abstract: A DC-DC converter system that can switch between BOOST and BUCK operation is used in a power failure prevention system. The DC-DC converter operates in BOOST mode at startup. It charges a storage capacitor via an inductor having its peak current controlled, together with a soft start ramp to limit the power supply in-rush current. During power failure, if the storage capacitor is charged above a pre-determined threshold and the input power supply discharges below a programmable threshold, the DC-DC converter switches from BOOST to BUCK mode, detectable through an internal power detection circuit; its output may also control an external/internal power switch that isolate the input main supply from the power bus. The BUCK mode converter will then dump the charges from the storage capacitor back to the power bus. The BOOST to BUCK mode seamless switchover is achieved through an analog/digital multiplexer that simplify the circuit implementation.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicants: PANASONIC ASIA PACIFIC PTE. LTD., PANASONIC CORPORATION
    Inventors: Yoshihito KAWAKAMI, Takuya ISHII, Hong Meng TANG, Chung Kiong Leslie KHOO, Tien Yew KANG, Jiong FU
  • Patent number: 8659514
    Abstract: LED drivers specially directed to LED matrix driver's ghost image prevention is disclosed. The LED driver receives an external input and decodes the input to produce a time multiplex timing on turning on an LED array. The LED driver inserts a dead time to the outputs and during this time the ghost image prevention circuit discharges the output stray capacitances to a predetermined level.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: February 25, 2014
    Assignees: Panasonic Corporation, Panasonic Semiconductor Asia Pte. Ltd.
    Inventors: Etsuji Sato, Atsushi Kitagawa, Yoshihito Kawakami, Chun Kiong Leslie Khoo, Ulysses Ramos Lopez, Narciso Repollo Semira, Jiong Fu
  • Publication number: 20120176062
    Abstract: LED drivers specially directed to LED matrix driver's ghost image prevention is disclosed. The LED driver receives an external input and decodes the input to produce a time multiplex timing on turning on an LED array. The LED driver inserts a dead time to the outputs and during this time the ghost image prevention circuit discharges the output stray capacitances to a predetermined level.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Applicants: PANASONIC SEMICONDUCTOR ASIA PTE., LTD., PANASONIC CORPORATION
    Inventors: Etsuji SATO, Atsushi KITAGAWA, Yoshihito KAWAKAMI, Chun Kiong Leslie KHOO, Ulysses Ramos LOPEZ, Narciso Repollo SEMIRA, Jiong FU
  • Patent number: 7772822
    Abstract: A power supply apparatus having a soft start function that enables a startup without any overshoot within an appropriate startup time regardless of whether the load is heavy or light. Even when output direct current voltage Vo has not yet risen upon startup, switch circuit (4) is turned ON within a count time of timer (7), and clamping circuit (5) clamps error signal (Ve) of error amplifier (2), so that an excessive signal is prevented from entering PWM circuit (6), and electric power supplied to load (13) is controlled. Consequently, supply power as the power supply apparatus is limited, and any inrush current can be prevented from being generated. By controlling the count time of timer (7) when this error signal is clamped, it is possible to realize a startup within an appropriate startup time without any overshoot.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihito Kawakami, Junji Ishiyama
  • Patent number: 7711870
    Abstract: An interface detecting circuit and interface detecting method are provided, whereby operations can be carried out depending on peripheral devices connected to USB terminals, and whereby the system can be simplified and software load can be reduced. A pull-down resistor is connected to an ID terminal of a Mini-A receptacle of a peripheral device, the voltage generated by the pull-down resistor, which is pulled down by the ID terminal of the Mini-A receptacle of the peripheral device, and a pull-up resistor, which is pulled up by the ID terminal of a Mini-B receptacle of a device, is detected in an analog fashion, using a detecting section comprised of comparators, and, via a logic section, a logic output is subjected to noise cancellation in a filter section and is memorized in a register section. The operations of other devices are determined according to the states memorized in the register section.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Masato Yoshida, Yoshihito Kawakami, Shigenori Arai, Hideyuki Kihara
  • Publication number: 20090198841
    Abstract: An interface detecting circuit and interface detecting method are provided, whereby operations can be carried out depending on peripheral devices connected to USB terminals, and whereby the system can be simplified and software load can be reduced. A pull-down resistor is connected to an ID terminal of a Mini-A receptacle of a peripheral device, the voltage generated by the pull-down resistor, which is pulled down by the ID terminal of the Mini-A receptacle of the peripheral device, and a pull-up resistor, which is pulled up by the ID terminal of a Mini-B receptacle of a device, is detected in an analog fashion, using a detecting section comprised of comparators, and, via a logic section, a logic output is subjected to noise cancellation in a filter section and is memorized in a register section. The operations of other devices are determined according to the states memorized in the register section.
    Type: Application
    Filed: February 6, 2008
    Publication date: August 6, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masato YOSHIDA, Yoshihito KAWAKAMI, Shigenori ARAI, Hideyuki KIHARA
  • Publication number: 20080218134
    Abstract: A power supply apparatus having a soft start function that enables a startup without any overshoot within an appropriate startup time regardless of whether the load is heavy or light. Even when output direct current voltage Vo has not yet risen upon startup, switch circuit 4 is turned ON within a count time of timer 7, and clamping circuit 5 clamps error signal Ve of error amplifier 2, so that an excessive signal is prevented from entering PWM circuit 6, and electric power supplied to load 13 is controlled. Consequently, supply power as the power supply apparatus is limited, and any inrush current can be prevented from being generated. By controlling the count time of timer 7 when this error signal is clamped, it is possible to realize a startup within an appropriate startup time without any overshoot.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihito KAWAKAMI, Junji ISHIYAMA