Patents by Inventor Yoshihito Nakamura

Yoshihito Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5231343
    Abstract: A driving apparatus for a stepping motor has first and second coils. The direction of the current flowing through each of the coils can be changed. A PWM-controlled stepping relay pulse generator is provided for imparting exciting current to the coils, and controls the duty factor of each stepping relay pulse at the rising and falling thereof.
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: July 27, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihito Nakamura
  • Patent number: 5177373
    Abstract: A digital circuit includes a flip-flop for latching N-bit digital data for a predetermined period of time, a counter for cyclically counting N-bit binary data, a first adding circuit for adding n of LSBs of the N-bit digital data and n MSBs of the N-bit binary data and for generating first PWM data, and a second adding circuit for adding N-n MSBs of the N-bit digital data and N-n LSBs of the N-bit binary data and for generating second PWM data. The second adding circuit is capable of, in accordance with the first PWM data, adding on a time-divisional basis PWM data corresponding to a signal having a pulse width of T/2 (N-n) (T is a time period of one cycle) to second PWM data items which are generated by the second adding circuit.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: January 5, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihito Nakamura
  • Patent number: 5138639
    Abstract: A pulse control circuit generates latch signals in response to edges of externally-input pulses and generates a resetting signal after each of the latch signals is generated. A pulse position measurement counter counts reference clock signals, thereby measuring the time interval between the generation of one latch signal and the generation of the succeeding latch signal. In response to the latch signal, a latch circuit latches the time interval measured by the pulse position measurement counter as output data. A pulse detector detects that the time interval between successive latch signals is shorter than a predetermined time. It also detects that the number of latch signals which have been input is larger than a predetermined number. A data control circuit is employed in association with the pulse detector.
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: August 11, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihito Nakamura