Patents by Inventor Yoshihumi Tahara

Yoshihumi Tahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8255198
    Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 28, 2012
    Assignee: Advantest Corporation
    Inventors: Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Mark Elston, Leon Chen, Toshiaki Adachi, Yoshihumi Tahara
  • Publication number: 20100192135
    Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 29, 2010
    Applicant: Advantest Corporation
    Inventors: Ramachandran KRISHNASWAMY, Harsanjeet SINGH, Ankan PRAMANICK, Mark ELSTON, Leon CHEN, Toshiaki ADACHI, Yoshihumi TAHARA
  • Publication number: 20080016396
    Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of
    Type: Application
    Filed: September 24, 2007
    Publication date: January 17, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
  • Publication number: 20080010524
    Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
  • Publication number: 20050039079
    Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of
    Type: Application
    Filed: March 31, 2004
    Publication date: February 17, 2005
    Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
  • Publication number: 20040225459
    Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
    Type: Application
    Filed: February 6, 2004
    Publication date: November 11, 2004
    Applicant: Advantest Corporation
    Inventors: Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Mark Elston, Leon Chen, Toshiaki Adachi, Yoshihumi Tahara