Abstract: A dynamic semiconductor memory includes a pair of complementary bit lines with a significant difference in load capacitance, storage capacitors and a pair of transistors for specifying one of the storage capacitors. One end of each storage capacitor is connected to one of the bit lines through one of the transistors and the other end is connected to the other bit line through the other transistor.

Abstract: A semiconductor memory device has an array of examined memory cells, and reference memory cells in a column. The examined memory cells in each column and the reference memory cells are connected with respective pairs of complementary bit lines connected with sense amplifiers. Each reference memory cell and the examined memory cells in each row are connected with corresponding word lines. The device also has a line data memory circuit, a bit line select circuit and a plurality of output evaluation circuits connected with the bit line pairs for the examined memory cells. In a test mode, identical data is simultaneously written to the reference and examined memory cells connected with each word line. The line data memory circuit outputs data from the reference memory cell as expected data, in response to which, the bit line select circuit selects one of the bit lines for each of the examined memory cells when the expected data is LOW, and the other of the bit lines when the expected data is HIGH.

Abstract: A semiconductor device such as a memory device has many sets of complementary data lines disposed parallel to one another. Mutually complementary lines are crossed with respect to each other nearly at the center such that their inter-line capacitances with a neighboring line are nearly equal. Crosstalks between either of the complementary word lines and such a neighboring line can be thereby reduced.

Abstract: A dynamic semiconductor memory comprises complementary bit lines for input and output of information, storage capacitors for storing information, and devices for specifying selected storage capacitors, each of the storage capacitors having one end connected to one end of the complementary bit lines and the other end to the other end of the complementary bit lines through one of the specifying devices to form a memory cell structure.

Abstract: A dynamic semiconductor memory comprising memory cells each including a pair of complementary bit lines, a storage capacitor and a device for selecting that capacitor. The memory further comprises a sense amplifier and a control device, and a greater differential voltage can be obtained from these bit lines by varying the ratio of their floating capacitance. Thus, the conventional requirement for balancing the complementary bit lines is eliminated and the lines can be formed in a multi-layer structure. This contributes significantly to making the memory cell areas smaller.