Abstract: Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

Abstract: The present invention increases the output voltage of a switching amplifier in a situation where the power supply voltage is limited. The switching amplifier includes first and second switches that are turned on and off in a complementary manner, and a capacitance, both ends of which serve as inputs to a power combiner. Both ends of the capacitance are connected to output ends of the first and second switches. The capacitance is supplied with power along with the operation of the first and second switches. As a result, an electric charge in the capacitance is used as a charge pump, and is used alternatingly for boosting or stepping down the output voltage depending on the operation frequency of the switching amplifier, thereby generating a rectangular voltage with a controlled wave height.

Abstract: Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

Abstract: Linearity is improved in an amplifier circuit without lowering gain. The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

Abstract: Duty signal ratio and signal generation circuits with clock signal duty ratio stabilization under decreased power supply conditions are disclosed. In one example, a duty ratio correction circuit includes an inverting buffer, a capacitor, a low pass filter, an error amplifier, and an adjusting unit. The capacitor adjusts the rising and falling times of an inverted signal output from the inverting buffer. The low pass filter extracts a low frequency component of the inverted signal. The error amplifier adjusts a duty ratio of the inverted signal by controlling at least one of an output source current and an output sink current of the inverting buffer on the basis of a difference between the extracted low frequency component and a reference signal. The adjusting unit adjusts the control of the inverting buffer by the error amplifier.

Abstract: Duty signal ratio and signal generation circuits with clock signal duty ratio stabilization under decreased power supply conditions are disclosed. In one example, a duty ratio correction circuit includes an inverting buffer, a capacitor, a low pass filter, an error amplifier, and an adjusting unit. The capacitor adjusts the rising and falling times of an inverted signal output from the inverting buffer. The low pass filter extracts a low frequency component of the inverted signal. The error amplifier adjusts a duty ratio of the inverted signal by controlling at least one of an output source current and an output sink current of the inverting buffer on the basis of a difference between the extracted low frequency component and a reference signal. The adjusting unit adjusts the control of the inverting buffer by the error amplifier.

Abstract: Linearity is improved in an amplifier circuit without lowering gain. The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

Abstract: A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.

Abstract: A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.