Patents by Inventor Yoshikatsu Kouhara
Yoshikatsu Kouhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8078423Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.Type: GrantFiled: September 21, 2007Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Takakazu Tokunaga, Kouichi Tanda, Hiroaki Shiraishi, Yoshikatsu Kouhara, Koji Takatomi
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Patent number: 7805688Abstract: A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.Type: GrantFiled: January 29, 2007Date of Patent: September 28, 2010Assignee: Fujitsu LimitedInventors: Noritoshi Yamakawa, Hiroaki Miyamoto, Yoshikatsu Kouhara, Akitsugu Nakayama, Kouichi Tanda
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Patent number: 7761822Abstract: A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion.Type: GrantFiled: March 14, 2008Date of Patent: July 20, 2010Assignee: Fujitsu LimitedInventors: Koji Takatomi, Kouichi Tanda, Hiroaki Shiraishi, Yoshikatsu Kouhara, Takakazu Tokunaga
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Patent number: 7735028Abstract: A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).Type: GrantFiled: September 18, 2007Date of Patent: June 8, 2010Assignee: Fujitsu LimitedInventors: Yoshinori Soejima, Yoshikatsu Kouhara, Hiroaki Shiraishi, Kouichi Tanda, Takakazu Tokunaga, Koji Takatomi
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Publication number: 20080235530Abstract: A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion.Type: ApplicationFiled: March 14, 2008Publication date: September 25, 2008Applicant: Fujitsu LimitedInventors: Koji Takatomi, Kouichi Tanda, Hiroaki Shiraishi, Yoshikatsu Kouhara, Takakazu Tokunaga
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Publication number: 20080097717Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.Type: ApplicationFiled: September 21, 2007Publication date: April 24, 2008Applicant: FUJITSU LIMITEDInventors: Takakazu Tokunaga, Kouichi Tanda, Hiroaki Shiraishi, Yoshikatsu Kouhara, Koji Takatomi
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Publication number: 20080077904Abstract: A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).Type: ApplicationFiled: September 18, 2007Publication date: March 27, 2008Applicant: FUJITSU LIMITEDInventors: Yoshinori Soejima, Yoshikatsu Kouhara, Hiroaki Shiraishi, Kouichi Tanda, Takakazu Tokunaga, Koji Takatomi
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Publication number: 20070217444Abstract: A computer capable of easily obtaining RTL of a TOP circuit after a block circuit is separated out of the TOP circuit. A port information input unit inputs the port information of the TOP circuit described in RTL, and the port information of block circuits composing the TOP circuit, from a user. A separation information input unit inputs separation information specifying a block circuit to be separated out of the TOP circuit, from the user. A separation port information creation unit creates separation port information after the block circuit is separated, by changing the port information of the TOP circuit and the block circuits based on the port information of the block circuit to be separated according to the separation information. An RTL rewriting unit rewrites RTL of the TOP circuit from which the block circuit has been separated, based on the separation port information created by the separation port information creation unit.Type: ApplicationFiled: February 28, 2007Publication date: September 20, 2007Applicant: FUJITSU LIMITEDInventors: Yoshikatsu Kouhara, Yoshinori Soejima, Hiroaki Shiraishi, Kouichi Tanda, Takakazu Tokunaga
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Publication number: 20070180213Abstract: A memory construction apparatus for automatically forming a logical memory space, thereby making it possible to design an integrated circuit efficiently. A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical conditions defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied.Type: ApplicationFiled: January 29, 2007Publication date: August 2, 2007Applicant: FUJITSU LIMITEDInventors: Noritoshi Yamakawa, Hiroaki Miyamoto, Yoshikatsu Kouhara, Akitsugu Nakayama, Kouichi Tanda