Abstract: A semiconductor device, which is daisy-chain connected with other semiconductor devices, includes a first communication section that receives reception data; a determining section that determines a type of the reception data, and that outputs a first and a second control signal according to the determination; a setting processing section that sets an address value based on the reception data and the second control signal, and that outputs a third control signal according to the setting of the address value; and a second communication section that includes a first input terminal to which the reception data is input, and an output terminal to which a communication line, that transmits transmission data to the other semiconductor devices, is connected, and that causes the first input terminal and the output terminal to be in connected or non-connected state based on the first or the third control signal.

Abstract: The invention provides a semiconductor device, which is daisy-chain connected with other semiconductor devices, including: a first communication section that receives reception data; a determining section that determines a type of the reception data, and that outputs a first and a second control signal according to the determination; a setting processing section that sets an address value based on the reception data and the second control signal, and that outputs a third control signal according to the setting of the address value; and a second communication section that includes a first input terminal to which the reception data is input, and an output terminal to which a communication line, that transmits transmission data to the other semiconductor devices, is connected, and that causes the first input terminal and the output terminal to be in connected or non-connected state based on the first or the third control signal.

Abstract: An electrical device includes a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate with each other through the communication line; and a control unit connected to one of the apparatus at an end stage thereof so that the control unit is configured to communicate with the one of the apparatus. The apparatus includes an address setting unit for setting a specific number to an address of the apparatus according to an address setting command when the apparatus receives address setting data including an address addition instruction as the address setting command for adding the specific number to the address of the apparatus. The apparatus further includes an address setting data transmission control unit for outputting the address setting data to a later stage apparatus when the address setting unit sets the specific value to the address of the apparatus.

Abstract: Provides a battery monitoring system including a battery cell number setting section that sets each LSI with the respectively individual number of battery cells C to which they are connected. When a command to sequentially measure the battery voltage of the battery cells is input, a cell selection control section compares the setting value with the commanded measurement start battery cell number. When the setting value is equal to or greater, performs measurement in sequence starting from the battery cell corresponding to the measurement start battery cell number. When the setting value is less, measurement is performed in sequence starting from the battery cell corresponding to the setting value. In a boost control section, during when the battery voltages with 3 higher potential battery cells is measured, a power source voltage is boosted by a charge pump and is supplied to first and second buffer amplifier.

Abstract: An electrical device includes a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate with each other through the communication line; and a control unit connected to one of the apparatus at an end stage thereof so that the control unit is configured to communicate with the one of the apparatus. The apparatus includes an address setting unit for setting a specific number to an address of the apparatus according to an address setting command when the apparatus receives address setting data including an address addition instruction as the address setting command for adding the specific number to the address of the apparatus. The apparatus further includes an address setting data transmission control unit for outputting the address setting data to a later stage apparatus when the address setting unit sets the specific value to the address of the apparatus.

Abstract: There is provided an image rendering processing apparatus including: a deriving section that, based on range data representing an image rendering range for performing image rendering, derives an image rendering region for each image rendering line configured by a plurality of pixels configuring an image; a determination section that, for each pixel in each of the image rendering lines, determines the density of the pixel according to the ratio of the image rendering region relative to the pixel region and according to the density of the image rendering region.

Abstract: A UART sets a predetermined threshold remaining data amount n, which defines an interrupt position, in a transmission trigger detector before data transmission is completed, checks if a trigger, which indicates the value of a read pointer RP or a count value N has reached a position indicated by the setting, has occurred and, if the trigger has occurred, causes a trigger detector to output a interrupt output control signal to an internal interrupt circuit to perform internal interrupt processing. Upon detecting this trigger, the internal interrupt circuit outputs an internal interrupt signal. When all data has not yet been transmitted from a transmission FIFO circuit, a CPU of a host controls the amount of data to be transferred to the transmission FIFO circuit, considering the threshold n, to prevent data in that circuit from being overwritten.

Abstract: A memory control circuit includes a watching circuit for observing a first request signal from an external device for accessing to a RAM and a second request signal, which has a priority higher than the first request signal, from a CPU for accessing to the RAM. The memory control circuit further includes a control circuit having an OR gate, an AND gate and a NOR gate. When the first and second request signals are inputted, it is scheduled that an operation based on the second access request signal is performed by the control circuit prior to that based on the first access request signal.

Abstract: A memory control circuit includes a watching circuit for observing a first request signal from an external device for accessing to a RAM and a second request signal, which has a priority higher than the first request signal, from a CPU for accessing to the RAM. The memory control circuit further includes a control circuit having an OR gate, an AND gate and a NOR gate. When the first and second request signals are inputted, it is scheduled that an operation based on the second access request signal is performed by the control circuit prior to that based on the first access request signal.

Abstract: A memory control circuit includes a watching circuit for observing a first request signal from an external device for accessing to a RAM and a second request signal, which has a priority higher than the first request signal, from a CPU for accessing to the RAM. The memory control circuit further includes a control circuit having an OR gate, an AND gate and a NOR gate. When the first and second request signals are inputted, it is scheduled that an operation based on the second access request signal is performed by the control circuit prior to that based on the first access request signal.

Abstract: A UART sets a predetermined threshold remaining data amount n, which defines an interrupt position, in a transmission trigger detector before data transmission is completed, checks if a trigger, which indicates the value of a read pointer RP or a count value N has reached a position indicated by the setting, has occurs and, if the trigger occurs, causes a trigger detector to output a interrupt output control signal to an internal interrupt circuit to perform internal interrupt processing. Upon detecting this trigger, the internal interrupt circuit outputs an internal interrupt signal. When all data has not yet been transmitted from a transmission FIFO circuit, a CPU of a host controls the amount of data to be transferred to the transmission FIFO circuit, considering the threshold n, to prevent data in that circuit from being overwritten.

Abstract: A memory control circuit includes a watching circuit for observing a first request signal from an external device for accessing to a RAM and a second request signal, which has a priority higher than the first request signal, from a CPU for accessing to the RAM. The memory control circuit further includes a control circuit having an OR gate, an AND gate and a NOR gate. When the first and second request signals are inputted, it is scheduled that an operation based on the second access request signal is performed by the control circuit prior to that based on the first access request signal.