Abstract: A digital switching system includes a multiplexer for multiplexing time slots from a plurality of circuits, a switching memory for storing and switching the multiplexed data for one frame period, switching control equipment for directing the interchange of the time slots stored in the switching memory in response to a switching request from an upper layer controller in a network, and a demultiplexer for demultiplexing into the plurality of circuits the time slot data as read out using address data supplied from the switching control equipment. The switching control equipment includes a control memory unit for writing connection information from the upper layer controller to either a first or a second control memory, and sequentially reading out the stored connection information in read-out order for the switching memory, and a selection unit for selecting read-out from either the first or the second control memory in response to the switching request.

Abstract: In a clock switching circuit, a write address is generated based on a pre-switched clock, and the write address is employed to store input data in memory. Then, a read address is generated based on a post-switched clock, and the read address is employed to read data from memory, so that a clock synchronized with the data is changed. There are multiple pre-switched frequencies, and the frequency of a post-switched clock is higher than the frequency of a pre-switched clock. When the pre-switched clock frequency is lower than the post-switched clock frequency, the read address is updated in accordance with a ratio of the frequency of the pre-switched clock to the frequency of the post-switched clock.