Patents by Inventor Yoshikazu Chigodo

Yoshikazu Chigodo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7245505
    Abstract: A laminated electronic component includes a laminated block in which a plurality of electrically insulating layers are laminated. An external conductor film is disposed on a surface of the laminated block. An additional conductor film which is at the same potential as the external conductor film is arranged such that it faces the external conductor film with an insulating layer disposed therebetween. The additional conductor film and the external conductor film are electrically connected to each other through a via-hole conductor so that they are at the same potential.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 17, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuhide Kato, Yoshikazu Chigodo, Keiji Ogawa
  • Publication number: 20040043190
    Abstract: A laminated electronic component includes a laminated block in which a plurality of electrically insulating layers are laminated. An external conductor film is disposed on a surface of the laminated block. An additional conductor film which is at the same potential as the external conductor film is arranged such that it faces the external conductor film with an insulating layer disposed therebetween. The additional conductor film and the external conductor film are electrically connected to each other through a via-hole conductor so that they are at the same potential.
    Type: Application
    Filed: August 5, 2003
    Publication date: March 4, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuhide Kato, Yoshikazu Chigodo, Keiji Ogawa
  • Patent number: 5507011
    Abstract: A transmitting circuit is connected to an antenna via a first diode. The antenna is connected to a receiving circuit with the circuit including a strip line and a second diode. Two diodes are turned ON by applying a positive voltage to a first control terminal. In this state, a signal from the transmitting circuit is transmitted from the antenna. The transmission signal is not transferred to the receiving circuit side due to a series resonance circuit with the inductance of the second diode and a capacitor. When the high-frequency switch is used for reception, a positive voltage is applied to a second control terminal. The voltage is divided by a resistors respectively connected to the diodes in parallel, and applied to the diodes as a backward voltage. And hence, the diodes are surely maintained in the OFF state. The isolation between the transmitting circuit and the antenna is improved by a parallel resonance circuit with the capacitance of the first diode and a inductor.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: April 9, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshikazu Chigodo, Harufumi Mandai
  • Patent number: 5495387
    Abstract: A plurality of capacitor elements defined by first and second capacitor electrodes are formed in the interior of a laminated ceramic block, while a plurality of first terminal electrodes to be electrically connected to the first capacitor electrodes and a ground terminal electrode to be connected to the second capacitor electrodes in common are formed on one side surface of the block. A plurality of resistor films are formed on a major surface of the block, to be connected to the first terminal electrodes. A plurality of second terminal electrodes are formed on another side surface of the block, to be electrically connected to the resistor films. Another ground terminal electrode is formed on this side surface, to be connected to the second capacitor electrodes in common. Thus, an RC array being applicable to a high frequency filter array is integrated and miniaturized to cope with high density packaging, as well as to enable surface mounting.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Kazuhiro Iida
  • Patent number: 5473293
    Abstract: A high-frequency switch includes a multi-layer board or a laminate. The laminate is formed by laminating many dielectric layers 14. First and second strip lines, capacitors and so on are provided inside the laminate. Each of the capacitors is formed by the combination of the dielectric layer and two capacitor electrodes which sandwich the dielectric layer. Also, first and second diodes and so on are mounted on the laminate. Furthermore, external electrodes are formed on portions of four sides of the laminate.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: December 5, 1995
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshikazu Chigodo, Harufumi Mandai
  • Patent number: 5237296
    Abstract: This composite electronic part comprises a dielectric layer on which earth electrodes are formed, a dielectric layer on which conductive lines are formed, and a dielectric layer on which electronic parts are pattern-formed. A plurality of the dielectric layers are so laminated that the dielectric layer with the earth electrodes is disposed next to the dielectric layer with the conductive lines. These conductive lines and earth electrodes form strip lines. A short-stub or an open-stub is formed by connecting one end of the conductive line to the earth electrode or opening that one end. A composite electronic part is obtained by connecting the short-stub, open-stub, and the electronic parts.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: August 17, 1993
    Assignee: Murata Manufacturing Co, Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Atsushi Tojo
  • Patent number: 5227739
    Abstract: A voltage controlled oscillator having a resonator wherein a substrate is made up of a plurality of dielectric layers; an inductor functioning conductive film and grounding electrode films are each formed at a boundary surface of one of the dielectric layers; the earth electrode films are arranged, in the direction in which the dielectric layers are laminated, at both sides of the conductor functioning conductive film; the inductor functioning conductive film and the grounding electrode films constitute the resonator; and electric lands are formed on the surface of the substrate so that other components of the oscillator are mounted on the surface of the substrate.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: July 13, 1993
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Keiji Asakawa, Yoshikazu Chigodo, Atsushi Inoue, Yo Funada
  • Patent number: 5187455
    Abstract: A delay line device for delaying signal transmission, comprising a dielectric layer, a grounding electrode layer disposed on one surface of the dielectric layer, a strip line conductor layer disposed on the other surface of the dielectric layer, an input terminal and an output terminal respectively connected to the strip line conductor layer at two positions, and a delay time adjusting electrode connected to at least one of the input and output terminals, a capacitance of which influences a delay time being obtained between the delay time adjusting electrode and the grounding electrode layer. The capacitance of the delay time adjusting electrode is adjustable, thereby permitting adjustment of the delay time.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: February 16, 1993
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Atsushi Tojo
  • Patent number: 5146191
    Abstract: A delay line device for delaying signal transmission. A lamination comprises an uppermost grounding electrode, a lowermost grounding electrode, a plurality of strip-line conductors, a plurality of intermediate grounding electrodes, dielectric layers, and protective layers. The strip-line conductors and the intermediate grounding electrodes are accumulated alternately and are interposed between the uppermost and the lowermost grounding electrodes. The dielectric layers are each interposed between each adjacent pair of the strip-line conductor and the intermediate grounding electrode. The protective layers are respectively provided on outer surfaces of the uppermost and the lowermost grounding electrodes. The strip-line conductors are connected via a through hole to form a strip-line conductor series and both ends of the series are extended onto a side surface of the lamination. An external input electrode is connected to one of the ends of the strip-line conductor series on the side surface of the lamination.
    Type: Grant
    Filed: June 10, 1991
    Date of Patent: September 8, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Atsushi Tojo
  • Patent number: 5093986
    Abstract: A method of forming bump electrodes, which is characterized in that conductive pastes are applied to a surface on which bump electrodes are to be formed, metal balls are made to adhere to the applied conductive pastes utilizing the viscosity of the conductive pastes before the conductive pastes are dried, and the conductive pastes and the metal balls are cofired.
    Type: Grant
    Filed: February 4, 1991
    Date of Patent: March 10, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Atsushi Tojyo
  • Patent number: 4795496
    Abstract: Adherent foreign matters such as metal powders and sludges are removed from the surface of work pieces of metal, ceramics or the like in a treating process thereof. Work pieces where foreign matters adhere and a granules composed of a heat-resisting inorganic substance such as sand are put together into a container. The inside of the container is heated to raise the temperature to the melting point of the adherents or to a temperature near it, and an external force is applied; to the container so that the work pieces will move in the container, for example, to rotate the container.
    Type: Grant
    Filed: January 29, 1986
    Date of Patent: January 3, 1989
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shintaro Karaki, Yoshikazu Chigodo, Masaaki Okane, Yukio Tanaka
  • Patent number: 4556929
    Abstract: A multi-layer ceramic capacitor includes a rectangular ceramic body with terminal electrodes provided on its opposite ends. A set of electrode, including a plurality of electrode layers, extends from one terminal electrode into the ceramic body. A similar set of electrode extends from the other terminal electrode into the ceramic body. The plurality of electrode layers have their edges arranged in tiers and, therefore, the equipotential surfaces appearing around the tip end of electrode layers can be dispersed.
    Type: Grant
    Filed: July 5, 1984
    Date of Patent: December 3, 1985
    Assignee: Murata Manufacturing Co. Ltd.
    Inventors: Yukio Tanaka, Yoshikazu Chigodo