Abstract: An NK cell showing higher cytotoxic activity is provided. An object of the present invention is to provide a pharmaceutical composition for NK cell therapies expected to be highly effective. The present invention provides an NK cell having the following characteristics of (1) and (2) or a population thereof: (1) the NK cell is CD16-positive, highly expresses CD56, and is CD57-negative, and (2) the NK cell is NKG2C-positive, is NKG2A-negative or lowly expresses NKG2A, and is CD94-positive. The present invention also provides a pharmaceutical composition containing a population of such NK cells, and a therapeutically effective amount of antibodies.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: The object of the invention is to stably bind an antibody to NK cells. A method for stabilizing binding of an antibody and an NK cell is provided, which method uses a substance having a region I that can bind to a surface protein of the NK cell, and a region II that can bind to the antibody. The substance may further contain a linker portion for linkage in addition to the region I and the region II.

Abstract: An NK cell showing higher cytotoxic activity is provided. An object of the present invention is to provide a pharmaceutical composition for NK cell therapies expected to be highly effective. The present invention provides an NK cell having the following characteristics of (1) and (2) or a population thereof. (1) the NK cell is CD16-positive, highly expresses CD56, and is CD57-negative, and (2) the NK cell is NKG2C-positive, is NKG2A-negative or lowly expresses NKG2A, and is CD94-positive. The present invention also provides a pharmaceutical composition containing a population of such NK cells, and a therapeutically effective amount of antibodies.

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

Abstract: A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, a word line connected to a gate of each of the memory cell transistors, a sequencer configured to control an operation of the memory cell array, and an input/output circuit. When the input/output circuit receives a command instructing an operation of continuously reading data of a plurality of pages from the memory cell transistors, the sequencer determines the data of the plurality of pages by continuously applying read voltages corresponding to the plurality of pages to be read, to the word line. In each continuous time period during which the control circuit applies read voltages for determining the data of one of the pages to the word line, the control circuit does not apply any read voltage for determining the data of another one of the pages to the word line.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to receive a first command set, receive a second command set related to a read operation while rejecting a command set related to a write operation or erase operation in response to the first command set, and execute the read operation on the memory cell array in response to the second command set.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to suspend a first operation on the memory cell array while the first operation is being performed, to start a first read operation on the memory cell array, and to resume the suspended first operation at least after the first read operation has been started. Upon receipt of a first command, a setting as to whether or not to resume the suspended first operation in response to receipt of a second command is switched. The second command is different from the first command.

Abstract: A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

Abstract: According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected in common to gates of the memory cells, and a control circuit configured to execute a read operation on the memory cells by applying a first read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the first read voltage and a second read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the second read voltage. The control circuit determines the first read voltage by applying at least first to third voltages to the word line, and determines the second read voltage based on the first read voltage.

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to receive a first command set, receive a second command set related to a read operation while rejecting a command set related to a write operation or erase operation in response to the first command set, and execute the read operation on the memory cell array in response to the second command set.

Abstract: A semiconductor memory device includes a memory transistor, a word line, a peripheral circuit, and electrodes connected to the peripheral circuit. In response to a write command via the electrodes, the peripheral circuit can execute a first program operation of applying a first program voltage to the word line one time when the write command is one of an n1-th write command to an n2-th write command corresponding to the memory transistor; and execute a second program operation of applying a second program voltage to the first word line at least one time when the write command is one of an (n2+1)-th write command to an n3-th write command corresponding to the memory transistor. The second program voltage in a k-th second program operation is less than the first program voltage in a k-th first program operation.