Abstract: A probe substrate for use in testing semiconductor devices can include a base substrate that can have first electrical terminals at a first pitch. One or more redistribution layers on the base substrate can include droplets of a conductive material that form redistribution traces extending from the first terminals to second electrical terminals at a second pitch different from the first pitch.

Abstract: A probe substrate for use in testing semiconductor devices can include a base substrate that can have first electrical terminals at a first pitch. One or more redistribution layers on the base substrate can include droplets of a conductive material that form redistribution traces extending from the first terminals to second electrical terminals at a second pitch different from the first pitch.

Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.

Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.

Abstract: In an electronic circuit such as MIS oscillation or amplifier circuit in which a MISFET or MISFET's is used as an amplifying element and a bias resistor is provided between input and output sides, a divided voltage of a power voltage determined by capacitive elements provided at the input side is selected to be equal to a bias voltage determined by the bias resistor, thereby preventing influence due to the variation in power voltage.

Abstract: A constant-current circuit has a depletion type FET and a series circuit consisting of an impedance element and an enhancement type FET connected in parallel between two terminals. The gate electrodes of the respective FET's are connected to a juncture between the impedance element and the enhancement type FET, and current which flows through the depletion type FET is set to be sufficiently larger than a current which flows through the series circuit. The voltage across the enhancement type FET is made substantially equal to a threshold voltage thereof, whereby the constant current characteristics of such constant-current circuits are checked from being dispersed.

Abstract: A key input circuit characterized in that a plurality of keys are divided into a plurality of key blocks, that a plurality of series of timing pulses of a first group are supplied to the respective key blocks, each series of timing pulses differing in phase from each other series of timing pulses, thereby to multiplex information on the respective keys of each key block, and that the multiplexed key information from the respective blocks is further multiplexed by a plurality of series of timing pulses of a second group, the timing pulses of the second group being longer in duration than the timing pulses of the first group.

Abstract: A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.

Abstract: In a logic circuit having a load MISFET of the depletion type, a MISFET logic circuit employs a logic block of a predetermined logic expression, and a MISFET of the enhancement type. The depletion type MISFET, the logic block and the enhancement type MISFET are connected in series. The enhancement type MISFET is driven by clock pulses so that, only when it is conductive, current flows through the series circuit. Thus, the amount of power consumption is lowered.