Patents by Inventor Yoshikazu Hirano

Yoshikazu Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11436391
    Abstract: A learning method and an automatic layout design method are disclosed. In one embodiment, provided is a learning method implementable by an apparatus for a system performing a layout design for automatically determining layout positions of a plurality of layout objects to be placed in a layout space by virtually moving the plurality of layout objects in the layout space based on a relationship between states of the plurality of layout objects in the layout space and movements of the plurality of layout objects to be performed, the method comprising: virtually moving a plurality of first layout objects in the layout space, determining a reward depending on whether or not the plurality of first layout objects interfere with another object in the layout space, and performing a learning process for learning the relationship through machine learning based on the reward.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: September 6, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshikazu Hirano
  • Publication number: 20220092228
    Abstract: A learning method and an automatic layout design method are disclosed. In one embodiment, provided is a learning method implementable by an apparatus for a system performing a layout design for automatically determining layout positions of a plurality of layout objects to be placed in a layout space by virtually moving the plurality of layout objects in the layout space based on a relationship between states of the plurality of layout objects in the layout space and movements of the plurality of layout objects to be performed, the method comprising: virtually moving a plurality of first layout objects in the layout space, determining a reward depending on whether or not the plurality of first layout objects interfere with another object in the layout space, and performing a learning process for learning the relationship through machine learning based on the reward.
    Type: Application
    Filed: December 4, 2019
    Publication date: March 24, 2022
    Inventor: Yoshikazu HIRANO
  • Patent number: 10299387
    Abstract: A substrate on which an electronic component is soldered, includes an electronic component, a through hole positioned on the substrate and passing through the substrate, a solder that joins the through hole and a terminal of the electronic component inserted in the through hole, a pattern formed on a first surface of the substrate, the first surface facing a second surface on which the electronic component is placed, a first resist superimposed on the pattern, an exposed portion of which the pattern is exposed from the first resist around the through hole, and a second resist superimposed on the pattern and arranged between the through hole and the exposed portion.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: May 21, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshikazu Hirano, Kinuko Mishiro, Toru Okada
  • Publication number: 20180343748
    Abstract: A substrate on which an electronic component is soldered, includes an electronic component, a through hole positioned on the substrate and passing through the substrate, a solder that joins the through hole and a terminal of the electronic component inserted in the through hole, a pattern formed on a first surface of the substrate, the first surface facing a second surface on which the electronic component is placed, a first resist superimposed on the pattern, an exposed portion of which the pattern is exposed from the first resist around the through hole, and a second resist superimposed on the pattern and arranged between the through hole and the exposed portion.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 29, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yoshikazu Hirano, KINUKO MISHIRO, Toru Okada
  • Publication number: 20170092451
    Abstract: A switch including a housing comprising a hole at a predetermined surface, an operating part disposed at the hole and configured to move with respect to the predetermined surface, a magnetic body configured to move in conjunction with the operating part, a magnetic sensor disposed in the housing and configured to detect magnetic force by the magnetic body, and a sheet disposed between the magnetic body and the operating part.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 30, 2017
    Applicant: KYOCERA Corporation
    Inventors: Takafumi SATO, Yoshikazu HIRANO
  • Patent number: 8701488
    Abstract: An electronic component analyzing apparatus is provided with a fixing part configured to hold a substrate to which an electronic component is soldered; a gripper configured to grip the electronic component; a transmission part coupled to the gripper, and configured to transmit an external force to the gripper as a force acting in a direction away from the substrate; and a support part configured to pivotally support the transmission part.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoshikazu Hirano, Mitsunori Abe, Takashi Fukuda
  • Patent number: 8656777
    Abstract: An electronic component analyzing apparatus is provided with a fixing part configured to hold a substrate to which an electronic component is soldered; a gripper configured to grip the electronic component; a transmission part coupled to the gripper, and configured to transmit an external force to the gripper as a force acting in a direction away from the substrate; and a support part configured to pivotally support the transmission part.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoshikazu Hirano, Mitsunori Abe, Takashi Fukuda
  • Patent number: 8429984
    Abstract: The present invention relates to a flow rate sensor 52 which causes a gas 80 included in a liquid 81 to travel in a piping 56, and which measures a flow speed of a sample by detecting the gas 80. The flow rate sensor 52 is configured to maintain a contact area of the gas with respect to the piping 56 at constant or at substantially constant.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: April 30, 2013
    Assignee: Arkray, Inc.
    Inventors: Noriaki Furusato, Yasumasa Honda, Daisuke Takahashi, Minoru Kotaki, Yoshikazu Hirano
  • Patent number: 8424391
    Abstract: The present invention relates to a method of adjusting a flow rate sensor 52 for measuring a travel time of a sample passing through a resistive body. The flow rate sensor 52 includes a straight tube 56, and plural photo sensors 52A to 52E for detecting interfaces 82A, 82B between a gas 80 and a liquid 81 traveling in the straight tube 56. Respective positions of the plural photo sensors 52A to 52E are adjusted by detecting the interfaces 82A, 82B by using such photo sensors 52A to 52E.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: April 23, 2013
    Assignee: Arkray, Inc.
    Inventors: Noriaki Furusato, Yasumasa Honda, Daisuke Takahashi, Minoru Kotaki, Yoshikazu Hirano
  • Patent number: 8338715
    Abstract: A printed circuit board provided with board electrodes, wherein each board electrode is provided with a board electrode base, for carrying by soldering a bottom electrode arranged at a bottom of an electronic device inside from outer edges of the electronic device, arranged inside from the outer edges of the electronic device and a projection projecting out from the board electrode base, narrower in width than the board electrode base, and connected to an interconnect of the printed circuit board.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Limited
    Inventors: Yoshikazu Hirano, Mitsunori Abe
  • Publication number: 20120017679
    Abstract: An electronic component analyzing apparatus is provided with a fixing part configured to hold a substrate to which an electronic component is soldered; a gripper configured to grip the electronic component; a transmission part coupled to the gripper, and configured to transmit an external force to the gripper as a force acting in a direction away from the substrate; and a support part configured to pivotally support the transmission part.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 26, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Yoshikazu HIRANO, Mitsunori ABE, Takashi FUKUDA
  • Publication number: 20110174081
    Abstract: The present invention relates to a method of adjusting a flow rate sensor 52 for measuring a travel time of a sample passing through a resistive body. The flow rate sensor 52 includes a straight tube 56, and plural photo sensors 52A to 52E for detecting interfaces 82A, 82B between a gas 80 and a liquid 81 traveling in the straight tube 56. Respective positions of the plural photo sensors 52A to 52E are adjusted by detecting the interfaces 82A, 82B by using such photo sensors 52A to 52E.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 21, 2011
    Applicant: ARKRAY, INC.
    Inventors: Noriaki Furusato, Yasumasa Honda, Daisuke Takahashi, Minoru Kotaki, Yoshikazu Hirano
  • Publication number: 20110162458
    Abstract: The present invention relates to a flow rate sensor 52 which causes a gas 80 included in a liquid 81 to travel in a piping 56, and which measures a flow speed of a sample by detecting the gas 80. The flow rate sensor 52 is configured to maintain a contact area of the gas with respect to the piping 56 at constant or at substantially constant.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 7, 2011
    Applicant: ARKRAY, INC.
    Inventors: Noriaki Furusato, Yasumasa Honda, Daisuke Takahashi, Minoru Kotaki, Yoshikazu Hirano
  • Publication number: 20110154888
    Abstract: The present invention relates to an analysis apparatus 1 comprising a resistive body 2 for giving a travel resistance to a sample, and power sources 33, 54 for giving power to cause the sample to pass through the resistive body 2. The power sources 33, 54 include a pressurizing mechanism 33 arranged at an upstream side of the resistive body 2 and a pressure-reduction mechanism 54 arranged at a downstream side of the resistive body. The pressurizing mechanism 33 and the pressure-reduction mechanism 54 are each a tube pump, for example. The resistive body 2 is provided with a plurality of minute fluid channels, for example.
    Type: Application
    Filed: September 17, 2009
    Publication date: June 30, 2011
    Applicant: ARKRAY, INC.
    Inventors: Noriaki Furusato, Yasumasa Honda, Daisuke Takahashi, Minoru Kotaki, Yoshikazu Hirano
  • Publication number: 20090056985
    Abstract: A printed circuit board provided with board electrodes, wherein each board electrode is provided with a board electrode base, for carrying by soldering a bottom electrode arranged at a bottom of an electronic device inside from outer edges of the electronic device, arranged inside from the outer edges of the electronic device and a projection projecting out from the board electrode base, narrower in width than the board electrode base, and connected to an interconnect of the printed circuit board.
    Type: Application
    Filed: August 4, 2008
    Publication date: March 5, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Yoshikazu Hirano, Mitsunori Abe
  • Patent number: 6482676
    Abstract: A method of mounting a semiconductor chip part on a substrate, which is capable of realizing high efficiency and high reliability of the mounting works. A leading end of a conductive wire is contact-bonded onto each pad of a semiconductor chip part, followed by tearing of the wire, to form a two-step bump having an upper step portion and a lower step portion larger in volume than the upper step portion. Only the upper step portions of the bumps are then brought in press-contact with a single flattening tool member having a flat surface in such a manner that heights of all of the bumps are made nearly equal to each other. A conductive paste is stuck on the bumps, and the substrate is coated with an adhesive. Thus, the semiconductor chip part is heated and pressurized onto the substrate by a mounting tool in such a state in which the pads are aligned with the corresponding lands of the substrate, to plastically deform the whole of the upper step portions and the lower step portions of the bumps.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Kazuhisa Tsunoi, Akira Fujii, Shunji Baba, Yoshikazu Hirano
  • Publication number: 20020048847
    Abstract: A method of mounting a semiconductor chip part on a substrate, which is capable of realizing high efficiency and high reliability of the mounting works. A leading end of a conductive wire is contact-bonded onto each pad of a semiconductor chip part, followed by tearing of the wire, to form a two-step bump having an upper step portion and a lower step portion larger in volume than the upper step portion. Only the upper step portions of the bumps are then brought in press-contact with a single flattening tool member having a flat surface in such a manner that heights of all of the bumps are made nearly equal to each other. A conductive paste is stuck on the bumps, and the substrate is coated with an adhesive. Thus, the semiconductor chip part is heated and pressurized onto the substrate by a mounting tool in such a state in which the pads are aligned with the corresponding lands of the substrate, to plastically deform the whole of the upper step portions and the lower step portions of the bumps.
    Type: Application
    Filed: July 1, 1997
    Publication date: April 25, 2002
    Inventors: KAZUHISA TSUNOI, AKIRA FUJII, SHUNJI BABA, YOSHIKAZU HIRANO