Abstract: A thin-film deposition system has a vacuum chamber and a plasma generator. The plasma generator includes a case, a cathode disposed in the case, an anode assembly disposed at an end of the case, a discharge power supply for applying a discharge voltage between the cathode and the anode assembly, and a gas supply means for supplying a discharge gas into the case. Electrons within a first plasma produced in the case are extracted into the vacuum chamber according to the discharge voltage. An evaporated material in a gaseous state inside the vacuum chamber is irradiated with electrons emitted from the plasma generator to produce a second plasma. The potential at the anode assembly is controlled by anode potential-controlling means such that the electrons within the second plasma are directed at the plasma generator and the ions within the second plasma are directed at the substrate.

Abstract: A thin-film deposition system has a vacuum chamber and a plasma generator. The plasma generator includes a case, a cathode disposed in the case, an anode assembly disposed at an end of the case, a discharge power supply for applying a discharge voltage between the cathode and the anode assembly, and a gas supply means for supplying a discharge gas into the case. Electrons within a first plasma produced in the case are extracted into the vacuum chamber according to the discharge voltage. An evaporated material in a gaseous state inside the vacuum chamber is irradiated with electrons emitted from the plasma generator to produce a second plasma. The potential at the anode assembly is controlled by anode potential-controlling means such that the electrons within the second plasma are directed at the plasma generator and the ions within the second plasma are directed at the substrate.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: It is judged whether or not the output voltages of a memory cell and a first reference cell, which is for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell, have reached their respective comparable levels, on the basis of the output voltages of first to third reference cells. After voltage values which can be compared with each other are obtained, the comparison result of the output voltage of the memory cell with the output voltage of the first reference cell is stored in a first latch circuit as the stored data of the memory cell, and the data is output via an output buffer. Thus, even when a reduction of an internal power supply voltage occurs, the data stored in the memory cell can be properly output.

Abstract: It is judged whether or not the output voltages of a memory cell and a first reference cell, which is for outputting a voltage at a first reference level to be compared with the output voltage of the memory cell, have reached their respective comparable levels, on the basis of the output voltages of first to third reference cells. After voltage values which can be compared with each other are obtained, the comparison result of the output voltage of the memory cell with the output voltage of the first reference cell is stored in a first latch circuit as the stored data of the memory cell, and the data is output via an output buffer. Thus, even when a reduction of an internal power supply voltage occurs, the data stored in the memory cell can be properly output.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns.

Abstract: An apparatus for quantitative secondary ion mass spectrometry comprising a sealed chamber for storing a sample containing a light impurity element which is to be analyzed, secondary ion generating means for bombarding a primary ion beam onto the sample so as to allow the sample to emit a secondary ion of the light element, and quantitative analyzing means for detecting the secondary ion so as to quantitatively analyze the light element contained in the sample. First evacuating means evacuates said sealed chamber to an ultrahigh vacuum during quantitative analysis. First cryopanel means is arranged to surround the sample, and first cooling means keeps said first cryopanel means at a cryogenic temperature during quantitative analysis so that said first cryopanel means adsorbs a gas present in said sealed chamber.