Patents by Inventor Yoshikazu Hosomura
Yoshikazu Hosomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090239Abstract: A semiconductor device includes a metal layer disposed above a transistor on a first substrate. The metal layer includes a first region extending in a first direction and a second region that has a width in the first direction smaller than the first region and protrudes from the first region in a second direction, and has a first corner portion having an angle larger than 180° as viewed in a third direction between a proximal end portion of the second region and the first region. The metal layer includes a first portion that is disposed within the first region and has a lower surface at a first height, and a second portion that is disposed within the second region and has a lower surface at a second height lower than the first height.Type: ApplicationFiled: March 1, 2023Publication date: March 14, 2024Applicant: Kioxia CorporationInventors: Kiichi TACHI, Ryota NIHEI, Yoshikazu HOSOMURA
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Publication number: 20240071478Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Kioxia CorporationInventors: Hideyuki KATAOKA, Yoshinao SUZUKI, Mai SHIMIZU, Kazuyoshi MURAOKA, Masami MASUDA, Yoshikazu HOSOMURA
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Publication number: 20230083392Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.Type: ApplicationFiled: February 24, 2022Publication date: March 16, 2023Inventors: Yoshikazu HOSOMURA, Hideyuki KATAOKA, Yoshinao SUZUKI, Mai SHIMIZU, Kazuyoshi MURAOKA, Masami MASUDA
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Patent number: 11114162Abstract: According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line; a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line; a common bit line; a first bit line transfer transistor; and a second bit line transfer transistor.Type: GrantFiled: March 6, 2020Date of Patent: September 7, 2021Assignee: Kioxia CorporationInventor: Yoshikazu Hosomura
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Publication number: 20210057028Abstract: According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line; a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line; a common bit line; a first bit line transfer transistor; and a second bit line transfer transistor.Type: ApplicationFiled: March 6, 2020Publication date: February 25, 2021Applicant: Kioxia CorporationInventor: Yoshikazu HOSOMURA
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Patent number: 8243524Abstract: A semiconductor storage device has a sense amplifier.Type: GrantFiled: March 15, 2010Date of Patent: August 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuya Suzuki, Toshiki Hisada, Yoshikazu Hosomura
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Publication number: 20100314771Abstract: A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line.Type: ApplicationFiled: March 15, 2010Publication date: December 16, 2010Inventors: Yoshikazu HOSOMURA, Toshiki Hisada, Fumiharu Nakajima, Chikaaki Kodama
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Publication number: 20100232225Abstract: A semiconductor storage device has a sense amplifier.Type: ApplicationFiled: March 15, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuya Suzuki, Toshiki Hisada, Yoshikazu Hosomura
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Patent number: 7646646Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.Type: GrantFiled: February 15, 2008Date of Patent: January 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshikazu Hosomura, Takuya Futatsuyama
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Publication number: 20080198667Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.Type: ApplicationFiled: February 15, 2008Publication date: August 21, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshikazu HOSOMURA, Takuya Futatsuyama