Patents by Inventor Yoshikazu Kasuya

Yoshikazu Kasuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930635
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 23, 2021
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20200258877
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 10679979
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20190035776
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 31, 2019
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 10121741
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 6, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9978737
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 22, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 9953922
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 24, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20170162498
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Publication number: 20170162499
    Abstract: A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Publication number: 20160358901
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 9455223
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: September 27, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20150155232
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 4, 2015
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 8984466
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20140110853
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: Seiko Epson Corporation
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 8637950
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 28, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 8418114
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 9, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20120246603
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 27, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 8214776
    Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 3, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Publication number: 20110239170
    Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Katsumi MORI, Kei KAWAHARA, Yoshikazu KASUYA
  • Patent number: 7977233
    Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya