Abstract: An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed. The signal processing portion includes a high breakdown voltage transistor circuit and a low breakdown voltage transistor circuit. The low breakdown voltage transistor circuit includes a depletion-type field effect transistor.

Abstract: An electronic device comprising a laminated structure including a first semiconductor chip and a second semiconductor chip is disclosed. In one example, the first semiconductor chip includes a sensor portion in which sensors are arranged, and the second semiconductor chip includes a signal processing portion in which signals obtained by the sensors are processed. The signal processing portion includes a high breakdown voltage transistor circuit and a low breakdown voltage transistor circuit. The low breakdown voltage transistor circuit includes a depletion-type field effect transistor.

Abstract: A semiconductor integrated circuit able to operate by different power supply voltages resulting from fluctuations in production, provided with a process monitor circuit for obtaining a grasp of a delay characteristic corresponding to the conditions of a production process, a memory circuit for storing data concerning an extent of process variation acquired by the process monitor circuit, and a power supply voltage control circuit for adaptively controlling the power supply voltage in accordance with the extent of process variation acquired by the process monitor circuit and stored in the memory circuit, and a test method for guaranteeing the operation of the semiconductor integrated circuit.

Abstract: An image processing apparatus which can reduce the power consumption by a large extent, wherein a predetermined shape to be displayed on a display is expressed by a composite of unit graphics by performing operations on a plurality of pixels simultaneously and by performing processing on valid results of operations for pixels positioned inside a unit graphic being processed. Clock enablers in operation sub-blocks judge the validity of the corresponding val data. Only operation sub-blocks receiving the corresponding val data indicating validity perform operations. Other operation sub-blocks do not perform operations. The operation blocks perform pipeline processing.

Abstract: A semiconductor integrated circuit able to operate by different power supply voltages resulting from fluctuations in production, provided with a process monitor circuit for obtaining a grasp of a delay characteristic corresponding to the conditions of a production process, a memory circuit for storing data concerning an extent of process variation acquired by the process monitor circuit, and a power supply voltage control circuit for adaptively controlling the power supply voltage in accordance with the extent of process variation acquired by the process monitor circuit and stored in the memory circuit, and a test method for guaranteeing the operation of the semiconductor integrated circuit.

Abstract: An image processing apparatus which can perform a variety of graphic processing using a video signal obtained by an image pickup apparatus. A system comprising a DDA set-up circuit for generating first image data and first z-data, a triangle circuit, a texture engine circuit, and a memory I/F circuit for writing the first image data and the first z-data respectively in a display buffer memory and a x-buffer memory and for writing the second image data and the second z-data respectively to the display buffer memory and the z-buffer memory when second image data corresponding to image pickup results of an image pickup apparatus and second x-data corresponding to the second image data are input from the video signal generator.

Abstract: A circuit board unit that has a number of data processing blocks and a programmable logic array that controls the operation of the processing blocks to perform respective processing operations includes an external self-diagnosis program storage device connected through an interface unit to the programmable logic array, so that when the program storage device is connected a self-diagnosis program is fed to the programmable logic array that then causes the processing blocks to perform a self-diagnosis operation.

Abstract: In an information data recording and reproducing device which can record and reproduce input information data accurately, an error correction code of the product sign format is added to the input information data to form coded data. The coded data are then NRZI converted and recorded onto a recording medium together with identification data of a predetermined data pattern. Error detecting and correcting are performed on data reproduced from the recording medium so as to obtain the data recorded on the recording medium.

Abstract: In an information transmitting device which transmits information in a preamble portion and a plurality of data blocks as a unitary set, when a block synchronizing code in the data blocks is detected, the timing of the detection and the block synchronizing code are determined to be correct or are subjected to error correction, and are utilized to reproduce information contained in the preamble portion.

Abstract: In an apparatus for transmitting digital data which includes information data and synchronous data having a plural-byte code arranged in a plural-byte code of the information data; the top bit position of the sync code is predicted by converting the transmitted digital data into parallel data at a desired timing and then comparing each byte of the parallel data with a particular byte of the sync code; and the sync code is detected in the transmitted digital data by first extracting, from the parallel data, a length corresponding to the plural-byte sync code starting from the predicted top bit position of the sync code and then comparing the extracted parallel data with the sync code.

Abstract: A relatively simplified sampling frequency converter for use in a format conversion apparatus is operative to convert sampled input data of an input sampling frequency into sampled output data of an output sampling frequency. The converter has an over-sampling circuit for increasing the sampling frequency of the sampled input data by a predetermined factor or coefficient to provide over-sampled data; an output data extractor for periodically extracting data from the over-sampled data in response to a timing pulse having the output sampling frequency; and a controller for controlling the phase of the timing pulse which controls the phase of the sampled output data.