Patents by Inventor Yoshikazu Miyanaga

Yoshikazu Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825739
    Abstract: A wireless receiving device removes signals of a redundant portion of each symbol of a transmission signal to extract signals of a data portion. The wireless receiving device linearly approximates, for each symbol, the overall variation in phase rotation of the symbol calculated by using the signals of the data portion to estimate the amount of phase rotation per time unit of the data portion. Subsequently, the wireless receiving device individually corrects each of the signals of the data portion according to the estimated amount of phase rotation per time unit to correct the signals of the data portion in a single symbol and over a plurality of symbols accordingly on a packet-by-packet basis. The signals of the data portion thus corrected are converted to subcarrier signals.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: November 21, 2017
    Assignee: RAYTRON, INC.
    Inventor: Yoshikazu Miyanaga
  • Publication number: 20170063500
    Abstract: A wireless receiving device removes signals of a redundant portion of each symbol of a transmission signal to extract signals of a data portion. The wireless receiving device linearly approximates, for each symbol, the overall variation in phase rotation of the symbol calculated by using the signals of the data portion to estimate the amount of phase rotation per time unit of the data portion. Subsequently, the wireless receiving device individually corrects each of the signals of the data portion according to the estimated amount of phase rotation per time unit to correct the signals of the data portion in a single symbol and over a plurality of symbols accordingly on a packet-by-packet basis. The signals of the data portion thus corrected are converted to subcarrier signals.
    Type: Application
    Filed: August 19, 2016
    Publication date: March 2, 2017
    Inventor: Yoshikazu MIYANAGA
  • Patent number: 8681905
    Abstract: A MIMO detector for use in MIMO-OFDM wireless communication that forms a plurality of propagation paths by using a plurality of transmitting and receiving antennas includes: an inverse matrix calculator operating as an inverse matrix calculation unit configured to calculate an inverse matrix of a matrix of the propagation path based on a signal received by a receiver; a detection speed controller operating as an estimation unit configured to estimate a variation in the propagation path over time; and a phase synchronization circuit and a regulator configured to variably control a processing time required to calculate the inverse matrix by the inverse matrix calculator, according to the variation in the propagation path over time estimated by the detection speed controller. The MIMO detector is provided on the side of the receiver of the wireless communication.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: March 25, 2014
    Assignee: RayTron, Inc.
    Inventors: Yoshikazu Miyanaga, Shingo Yoshizawa
  • Publication number: 20120269301
    Abstract: A MIMO detector for use in MIMO-OFDM wireless communication that forms a plurality of propagation paths by using a plurality of transmitting and receiving antennas includes: an inverse matrix calculator operating as an inverse matrix calculation unit configured to calculate an inverse matrix of a matrix of the propagation path based on a signal received by a receiver; a detection speed controller operating as an estimation unit configured to estimate a variation in the propagation path over time; and a phase synchronization circuit and a regulator configured to variably control a processing time required to calculate the inverse matrix by the inverse matrix calculator, according to the variation in the propagation path over time estimated by the detection speed controller. The MIMO detector is provided on the side of the receiver of the wireless communication.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 25, 2012
    Applicant: RayTron, Inc.
    Inventors: Yoshikazu Miyanaga, Shingo Yoshizawa
  • Publication number: 20120102083
    Abstract: A Fourier transform processor that is used in wireless communication includes: a Fourier transform mechanism including a butterfly unit and configured to perform a Fourier transform on data that is input to the Fourier transform processor; a first memory configured to store the data that is input to the Fourier transform mechanism; a first commutator configured to rearrange the data that is input to the first memory; and a second commutator configured to rearrange the data that is output from the first memory and that is input to the butterfly unit. This configuration allows the size and power consumption of the Fourier transform processor to be reduced.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 26, 2012
    Applicant: RayTron, Inc.
    Inventors: Yoshikazu Miyanaga, Shingo Yoshizawa
  • Patent number: 7650131
    Abstract: A wireless receiver which is used for a digital signal transmission system to wirelessly transmit a digital signal by packetizing and modifying it, selectively sets the shortest arithmetical bit length satisfying a required communication quality when performs demodulation arithmetical processing to demodulate a digital signal to be packet-transmitted, inputs a demodulation arithmetical result by the arithmetical bit length to calculate an error vector magnitude value that is a measure indicating a difference between the arithmetical result and a known ideal result, predicts a bit error rate by using the EVM value as an evaluation criterion, selects an arithmetical bit length by which the bit error rate becomes optimum, and executes the demodulating arithmetical processing by the selected arithmetical bit length.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: January 19, 2010
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shingo Yoshizawa, Yoshikazu Miyanaga, Masaki Hirata
  • Publication number: 20070226289
    Abstract: A wireless receiver which is used for a digital signal transmission system to wirelessly transmit a digital signal by packetizing and modifying it, selectively sets the shortest arithmetical bit length satisfying a required communication quality when performs demodulation arithmetical processing to demodulate a digital signal to be packet-transmitted, inputs a demodulation arithmetical result by the arithmetical bit length to calculate an error vector magnitude value that is a measure indicating a difference between the arithmetical result and a known ideal result, predicts a bit error rate by using the EVM value as an evaluation criterion, selects an arithmetical bit length by which the bit error rate becomes optimum, and executes the demodulating arithmetical processing by the selected arithmetical bit length.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 27, 2007
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Shingo Yoshizawa, Yoshikazu Miyanaga, Masaki Hirata
  • Publication number: 20020169607
    Abstract: The speech recognition device, which can realize speech recognition with a small-scaled circuit, has been disclosed. The speech recognition device comprises the similarity circuit, which receives speech input signals and puts out characteristics based on the self-organizing algorithm, and the matrix circuit that performs the matrix operations of the output signal, wherein: the similarity circuit comprises a circuit that calculates distances between plural multi-dimensional input vectors and the pattern vectors prepared in advance, calculates a value corresponding to one dimension using a pair of neuron MOSFETS, and forms a voltage signal in accordance with the degree of similarity by summing up the current that flows in each neuron MOSFET; and the matrix circuit, in which capacitors corresponding to weighting operations are arranged in matrix, receives a voltage signal in accordance with the degree of similarity and outputs what is most similar, to the patterns prepared in advance.
    Type: Application
    Filed: December 27, 2001
    Publication date: November 14, 2002
    Inventors: Yoshikazu Miyanaga, Masayuki Kabasawa