Patents by Inventor Yoshikazu Nakata

Yoshikazu Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6620650
    Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: September 16, 2003
    Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.
    Inventors: Yoshikazu Nakata, Takeshi Kasai
  • Publication number: 20030036229
    Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.
    Type: Application
    Filed: October 23, 2002
    Publication date: February 20, 2003
    Inventors: Yoshikazu Nakata, Takeshi Kasai
  • Patent number: 6495394
    Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 17, 2002
    Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.
    Inventors: Yoshikazu Nakata, Takeshi Kasai
  • Patent number: 6249053
    Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: June 19, 2001
    Assignee: Sumitomo Metal (SMI) Electronics Devices Inc.
    Inventors: Yoshikazu Nakata, Takeshi Kasai
  • Patent number: 6074893
    Abstract: A process for forming fine thick-film conductor patterns on a ceramic substrate which comprises the steps of forming grooves in a positive-working photoresist layer on the substrate by the photolithographic technology, filling the grooves with a conductive paste by squeezing with a squeegee, removing the photoresist layer by a wet process, and firing the remaining conductive paste pattern is improved. By the improvements, the conductive paste is squeezed into the grooves by the screen printing technique using a mask, and/or the solvent in the conducive paste consists essentially of one or more hydrocarbons, and/or the squeegee is made of a material having a flexural modulus in a range of 30-200 kgf/mm.sup.2. The formation of the grooves may be accomplished by laser beam machining; in this case a negative-working photoresist or any other soluble resin may be used to form the grooves therein.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: June 13, 2000
    Assignees: Sumitomo Metal Industries, Ltd., Sumitomo Metal Ceramics Inc.
    Inventors: Yoshikazu Nakata, Syozo Otomo, Kazunari Tanaka, Koichi Uno