Abstract: The server device includes a first storage unit that stores an application divided into sub-applications, a second storage unit that stores information for each sub-application; a third storage unit that stores user information, a fourth storage unit that stores prepayment information, and a control unit that controls the entire server device. Some of the sub-applications can be executed alone. The control unit receives a send request from a user, and sends the sub-application through a data communication path. The user terminal which received the sub-application can start execution thereof immediately. Thus, an application communication system allowing utilization of a desired application in a short period of time after the start of communication is provided.

Abstract: Method and apparatus are described for generating more accurate and timely FIFO status flags. Preferably, the asynchronous FIFO read and write pointers are conventionally compared with one another and the output of such comparison is glitch-suppressed. During such operation in accordance with the invented method and apparatus, prediction signals are used to precondition the status flag output latches so that they will provide the earliest possible accurate status reflecting asynchronous read and write clock activity. If a boundary condition is present--e.g. depending upon the next read or write clock activity, the FIFO's half full status flag may change where such change is impossible to predict because it is unknowable whether the next operation will be a read or a write or both--then an asynchronous state machine takes over from the prediction flag logic to ensure accurate and early preconditioning of the status flags' output latches.

Abstract: A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction; and a clock generator supplied with the output of an oscillator for developing a basic clock of a desired waveform for supply to the system, wherein the basic clock is developed or inhibited when the control signal is supplied from the clock control signal generator.