Patents by Inventor Yoshikazu Oikawa

Yoshikazu Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9877390
    Abstract: A multilayer substrate including a multilayer body formed by laminating a plurality of insulating layers including via holes in the insulating layer as an uppermost layer of the multilayer body so as to pass through the insulating layer, and via conductors formed by filling the via holes with a conductive paste. The via holes are formed through lower end positions, upper end positions, and intermediate positions between the lower end positions and the upper end positions such that a diameter enlargement degree toward the upper end positions from the intermediate positions is larger than a diameter enlargement degree toward the intermediate positions from the lower end positions. By forming the via holes as described above, when the via holes are filled with the conductive paste from openings at the small diameter side of the via holes, exudation of the conductive paste from openings at the large diameter side is prevented.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 23, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuhiko Takemura, Kazuhiro Isebo, Yutaka Fukuda, Yoshikazu Oikawa
  • Publication number: 20160242287
    Abstract: A multilayer substrate including a multilayer body formed by laminating a plurality of insulating layers including via holes in the insulating layer as an uppermost layer of the multilayer body so as to pass through the insulating layer, and via conductors formed by filling the via holes with a conductive paste. The via holes are formed through lower end positions, upper end positions, and intermediate positions between the lower end positions and the upper end positions such that a diameter enlargement degree toward the upper end positions from the intermediate positions is larger than a diameter enlargement degree toward the intermediate positions from the lower end positions. By forming the via holes as described above, when the via holes are filled with the conductive paste from openings at the small diameter side of the via holes, exudation of the conductive paste from openings at the large diameter side is prevented.
    Type: Application
    Filed: April 28, 2016
    Publication date: August 18, 2016
    Inventors: Kazuhiko Takemura, Kazuhiro Isebo, Yutaka Fukuda, Yoshikazu Oikawa
  • Patent number: 7847197
    Abstract: A multilayer circuit board includes a laminate having a plurality of ceramic layers, and a wiring pattern disposed in the laminate, wherein a ceramic layer includes, as the wiring pattern, a fully penetrating via-hole conductor that vertically passes through the ceramic layers, and a serial partially penetrating via-hole conductor that is electrically connected to the fully penetrating via-hole conductor in the ceramic layers and does not pass completely through the ceramic layers.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: December 7, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshikazu Oikawa, Takayoshi Yoshikawa
  • Publication number: 20080093117
    Abstract: A multilayer circuit board includes a laminate having a plurality of ceramic layers, and a wiring pattern disposed in the laminate, wherein a ceramic layer includes, as the wiring pattern, a fully penetrating via-hole conductor that vertically passes through the ceramic layers, and a serial partially penetrating via-hole conductor that is electrically connected to the fully penetrating via-hole conductor in the ceramic layers and does not pass completely through the ceramic layers.
    Type: Application
    Filed: January 3, 2008
    Publication date: April 24, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshikazu OIKAWA, Takayoshi YOSHIKAWA