Patents by Inventor Yoshikazu SABETTO
Yoshikazu SABETTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240039853Abstract: A communication device to be coupled to a transmission device with MC-LAG, the communication device includes a first output port coupled to an other communication device within a first route, a second output port within a second route, an iTAS device arranged in each of the first output port and the second output port, and configured to preferentially output a high priority flow, based on a set an iTAS period, a memory, and a processor coupled to the memory and configured to acquire a first iTAS period set to the iTAS device arranged in the first output port and a second iTAS period set to an iTAS device arranged in a third output port in the other communication device within the first route, and set an iTAS period of the iTAS device arranged in the second output port, based on the first and second iTAS periods.Type: ApplicationFiled: June 1, 2023Publication date: February 1, 2024Applicant: Fujitsu LimitedInventors: Norikazu HIKIMOCHI, Kazuto NISHIMURA, Shoji MIYAKE, Jiro TAKEZAWA, Yoshikazu SABETTO
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Patent number: 11711304Abstract: A packet switch that determines a time slot for closing transmission of low-priority packets based on a determination result of periods of high-priority packets having periodicity, the packet switch includes: a memory; and a processor coupled to the memory and configured to: determine, for respective input ports, the periods of the input high-priority packets; and determine a setting period of a gate control list in which the time slot for closing is set, based on the determined periods of the high-priority packets.Type: GrantFiled: April 20, 2021Date of Patent: July 25, 2023Assignee: FUJITSU LIMITEDInventor: Yoshikazu Sabetto
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Patent number: 11700634Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.Type: GrantFiled: May 3, 2021Date of Patent: July 11, 2023Assignee: FUJITSU LIMITEDInventors: Norikazu Hikimochi, Kazuto Nishimura, Yoshikazu Sabetto
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Publication number: 20220022200Abstract: A packet switch includes a memory, and a processor coupled to the memory and configured to learn a pattern of a high-priority packet having a cyclicity, monitor a burst end point of the high-priority packet, based on a result of the learning, detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes, and determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.Type: ApplicationFiled: May 3, 2021Publication date: January 20, 2022Applicant: FUJITSU LIMITEDInventors: NORIKAZU HIKIMOCHI, Kazuto Nishimura, Yoshikazu Sabetto
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Publication number: 20220021619Abstract: A packet switch that determines a time slot for closing transmission of low-priority packets based on a determination result of periods of high-priority packets having periodicity, the packet switch includes: a memory; and a processor coupled to the memory and configured to: determine, for respective input ports, the periods of the input high-priority packets; and determine a setting period of a gate control list in which the time slot for closing is set, based on the determined periods of the high-priority packets.Type: ApplicationFiled: April 20, 2021Publication date: January 20, 2022Applicant: FUJITSU LIMITEDInventor: Yoshikazu Sabetto
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Patent number: 11228540Abstract: A communication device includes: multiple queues, each of which stores a packet; an input section that inputs a concerned packet to a queue that is among the multiple queues and corresponds to a priority of the concerned packet; an adder that acquires first time when the concerned packet is input to the queue corresponding to the priority, and that adds the first time to the concerned packet; a reader that reads packets from each of the multiple queues in order from a packet with the highest priority; a calculator that acquires second time when the concerned packet is read from the queue corresponding to the priority, and that calculates delay time of the concerned packet from the difference between the first time and the second time; and a priority controller that increases the priority of the concerned packet based on the delay time.Type: GrantFiled: March 3, 2020Date of Patent: January 18, 2022Assignee: FUJITSU LIMITEDInventor: Yoshikazu Sabetto
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Publication number: 20200304431Abstract: A communication device includes: multiple queues, each of which stores a packet; an input section that inputs a concerned packet to a queue that is among the multiple queues and corresponds to a priority of the concerned packet; an adder that acquires first time when the concerned packet is input to the queue corresponding to the priority, and that adds the first time to the concerned packet; a reader that reads packets from each of the multiple queues in order from a packet with the highest priority; a calculator that acquires second time when the concerned packet is read from the queue corresponding to the priority, and that calculates delay time of the concerned packet from the difference between the first time and the second time; and a priority controller that increases the priority of the concerned packet based on the delay time.Type: ApplicationFiled: March 3, 2020Publication date: September 24, 2020Applicant: FUJITSU LIMITEDInventor: Yoshikazu Sabetto
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Publication number: 20150063127Abstract: There is provided a transmission apparatus which includes a transmission unit configured to transmit a control data to an opposite transmission apparatus at a transmission interval, a first determination unit configured to determine a communication quality of a network connected with the opposite transmission apparatus, and an adjustment unit configured to adjust the transmission interval, at which the control data is transmitted, to be longer than a reference transmission interval when the communication quality is equal to or greater than a predetermined value.Type: ApplicationFiled: July 23, 2014Publication date: March 5, 2015Applicant: FUJITSU LIMITEDInventors: Yoshikazu Sabetto, Fusae Yamanouchi
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Publication number: 20120300637Abstract: A CPU 16 of a transmission apparatus 2 determines whether reception processing of a CCM frame received from an opposite MEP transmission apparatus 2 is in a congestion state. When the reception processing is in a congestion state, the CPU 16 calculates an adjustment amount for adjusting transmission timing of a CCM frame related to the opposite MEP transmission apparatus 2 so as to decentralize reception processing of CCM frames. The CPU 16 adds the calculated adjustment amount into a CCM frame to be transmitted to a source MEP transmission apparatus 2, and transmits the CCM frame to the source MEP transmission apparatus 2. In case of receiving an adjustment amount from another opposite MEP transmission apparatus 2, the CPU 16 adjusts transmission timing of a CCM frame to be transmitted to the opposite transmission apparatus 2 on the basis of the adjustment amount.Type: ApplicationFiled: March 23, 2012Publication date: November 29, 2012Applicants: FUJITSU TELECOM NETWORKS LIMITED, FUJITSU LIMITEDInventors: Yoshikazu SABETTO, Yukihide Yamasaki, Mayumi Tsuru