Patents by Inventor Yoshikazu Suzumura

Yoshikazu Suzumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6871159
    Abstract: An occupant weight detecting device includes a load detecting means equipped to a seat body for detecting a load applied to the seat body, a calculating means for calculating an initial load value during the seat body under an initial condition based upon a detected load value by the load detecting means and for calculating a value of an occupant load applied to the seat body by subtracting the initial load value from the detected load value, and a filter housed in the calculating means and possessing a cutoff frequency so as to attenuate a fluctuation of the detected load value generated due to an element other than a deterioration inherent to the load detecting means.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 22, 2005
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Katsu Hattori, Morio Sakai, Yukihiro Yamamoto, Masaki Mori, Yoshikazu Suzumura
  • Publication number: 20030216886
    Abstract: An occupant weight detecting device includes a load detecting means equipped to a seat body for detecting a load applied to the seat body, a calculating means for calculating an initial load value during the seat body under an initial condition based upon a detected load value by the load detecting means and for calculating a value of an occupant load applied to the seat body by subtracting the initial load value from the detected load value, and a filter housed in the calculating means and possessing a cutoff frequency so as to attenuate a fluctuation of the detected load value generated due to an element other than a deterioration inherent to the load detecting means.
    Type: Application
    Filed: March 7, 2003
    Publication date: November 20, 2003
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Katsu Hattori, Morio Sakai, Yukihiro Yamamoto, Masaki Mori, Yoshikazu Suzumura
  • Patent number: 4718101
    Abstract: A segmentation apparatus utilized in an image processing system for recognizing a pattern in an image inputted thereto includes a separate circuit for outputting logical values of m by n pixels separated from the inputted image, an encode circuit for storing in advance therein codes to be determined according to the content of an inputted pattern and for outputting a code indicating that which set of pixels is identical to the objective pixel by using as an input pattern the logical value outputted from the separate circuit, and a select circuit for selecting a label of the objective label, from the label data of neighborhood pixels already determined and the new label data assigned, in accordance with the output from the encode circuit.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: January 5, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Ariga, Seiji Hata, Yoshikazu Suzumura, Masaaki Nakagima, Michio Takahashi
  • Patent number: 4315199
    Abstract: Disclosed is a control circuit of a positioning device for moving a member to be controlled to a predetermined position by using a d-c motor, in which there are used arithmetic circuit means for detecting a difference signal, to be converted to a driving signal of the motor, between the position detecting signal of the member and the reference signal of the predetermined position, and correcting circuit means coupled to the arithmetic circuit means for causing the difference signal to be small, whereby the motor is free from the hunting phenomenon.
    Type: Grant
    Filed: August 3, 1979
    Date of Patent: February 9, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Ryuichi Kyomasu, Shuichi Hanashima, Yoshikazu Suzumura
  • Patent number: 4044344
    Abstract: In a MIS dynamic memory, information is written in the memory cell at a predetermined address, the access to other plural addresses is made for a fixed time period under such a condition that the memory cell of the predetermined address is not refreshed, and the stored information is thereafter read out of the memory cell of the predetermined address. The level of the read information is compared with a predetermined threshold value, thereby determining the information hold time of the memory cell.
    Type: Grant
    Filed: May 12, 1976
    Date of Patent: August 23, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Hidetsugu Wada, Yoichi Asano, Yoshikazu Suzumura
  • Patent number: 3962687
    Abstract: In a method of inspection of a semiconductor memory device, selection signals for selecting a memory cell to be tested and a designation signal for designating the address of a predetermined memory cell are compared, to produce a mask instruction signal when the address of the memory cell to be tested is coincident with the address of the predetermined memory cell, and the judgment of the test result of the predetermined memory cell is masked by the mask instruction signal. If the predetermined memory cell is one known to be inferior during the wiring check, it will be also defection during the test of any characteristic. Since such memory cells with inferior wiring are masked in characteristic tests, the analysis of defects is facilitated.
    Type: Grant
    Filed: October 15, 1974
    Date of Patent: June 8, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Suzumura, Yoichi Asano