Abstract: A prefix corresponding to a data block at the head of each of data groups in data of a layer 3 of a received FM multiplex broadcast program and data of a layer 4 of the received FM multiplex broadcast program are stored in first storage means. When a data retention command is entered, the data of the layer 3 is produced on the basis of the prefix and the data of the layer 4 which are stored in the first storage means, and the produced data of the layer 3 is retained in second storage means as versatile recording and reproducing data.

Abstract: In a receiver in a data broadcasting system, a receiver in a second data broadcasting system according to the present invention is characterized by comprising judging device for judging whether or not program data constituting at least one of received programs has been updated, and switching device for switching, when it is judged by the judging device that the program data has been updated, a program to be displayed into the program whose program data updating has been performed.

Abstract: The credit card information management system checks the creditability of a credit card intended to be used for purchase of goods or service by using the card information owned by member stores of credit companies. A host computer of the card management center outputs information regarding the validity or invalidity of a credit card of a customer member of a credit company as card information, a transmission facility wirelessly transmits digital data of the card information. A receiving facility of a member store receives radio signals of the card information and checks whether or not there is any missing of data. If any missing occurs, a transfer of the missed data is requested to the host computer.

Abstract: An FM multiplexed broadcasting signal received by an antenna and FM-demodulated by an FM tuner portion is demodulated by a demodulation LSI into a digital signal corresponding to packet data. The digital signal is successively supplied by every packet to a CPU of a receiving portion. The CPU of the receiving portion removes unnecessary data of the received data and then supplies only data required for a CPU of a personal computer via a buffer without delay from the reception. When a transferred packet is a successive reproduction program packet or a time information packet, the CPU of the personal computer calculates latency required before a predetermined data analysis processing is started, and performs data analysis processing in an elapse of the latency. Responsively, reconfiguration of program data is performed and corresponding character information or the like is output to a displaying portion.

Abstract: A system for managing sales of goods for vending machines includes a goods control center, a plurality of vending machines, and terminal computers equipped in the respective vending machines. The goods control center includes a host computer for preparing digital data signals as control instructions, and a frequency moderation sub-carrier broadcasting facility as a transmission facility for outputting the digital data signals. Each vending machine has a receiving facility for receiving the digital data signals from the goods control center, and a responding facility. Each terminal computer receives the digital data signals and selectively extracts the digital data as the control instructions necessary for the vending machine to thereby store the digital data necessary for the vending machine in a memory.

Abstract: An FM multiple radio broadcasting receiver includes a data group number and data packet number derivation circuit by which a data group number and a data packet number included in a prefix of FM subcarrier data are derived. A first random number generator generates a first random number on the basis of the data group number, the data packet number and scramble key data which is outputted from a scramble key generation circuit, and sets the first random number in a second random number generator as its initial value. Therefore, it is possible to appropriately scramble or descramble with using packet structure of the FM subcarrier data.

Abstract: A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.

Abstract: In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.

Abstract: In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

Abstract: An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful.

Abstract: A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

Abstract: An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set.