Abstract: A detector of an oscillation stopping, which detects the stopping of the oscillation of external clock 11, without increasing the load of CPU 45 in the micro computer 40, and generates a signal to reset the micro computer or exchanges the system clock from the external clock to an inner clock. In an embodiment, one shot pulse is generated for every standing up and/or down edge of the external clock. A capacitor of the charge-discharge circuit is charged and discharged at every one shot pulse. The voltage of the charge-discharge circuit is watched by a Schmitt circuit. When the voltage of the charge-discharge circuit exceeds a predetermined voltage, a signal for resetting the micro computer is generated. In another embodiment, an inner clock oscillation circuit, comprised of a ring oscillator, for example, is actuated, when the voltage of the charge/discharge circuit exceeds a predetermined voltage, and the system clock of the micro computer is exchanged to the inner clock from the external clock.

Abstract: The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.

Abstract: A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.

Abstract: A high-speed microcomputer having a condition decision circuit in which a signal output indicating whether or not a branch condition is satisfied is always active by taking out only a necessary bit by a mask register value after comparing a register value and a compare register value for every bit.

Abstract: A single-chip microcomputer (5) for controlling a peripheral circuit (7) having a constant process speed regardless of its process contents, is provided with a counter (2) for counting to a predetermined count so that a frequency of the clock signal is divided by the count and used as an operation clock for controlling the peripheral circuit.

Abstract: A pulse-signal extracting method and apparatus which are capable of generating an accurate pulse output even if the pulse input signal greatly pulsates due to a low-frequency noise component. A predetermined offset voltage is added to the input signal where the low-frequency noise component is superimposed on a pulse waveform which is the signal component so as to obtain an amplified signal. This amplified signal is inputted to a low-pass filter so as to output only the amplified flow-frequency component, and the original input signal is compared with the amplified low-frequency component in a comparator so as to extract the pulse waveform, which is the signal component, on the basis of the comparison result.