Patents by Inventor Yoshiki Hamada
Yoshiki Hamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240114799Abstract: A piezoelectric substrate according to the present disclosure includes: a base body; an electrode formed at the base body; and a piezoelectric layer formed at the electrode and containing potassium, sodium, and niobium. A value of IR2/IR1 obtained by dividing an integrated intensity IR2 at a peak 2 by an integrated intensity IR1 at a peak 1, when a surface of the piezoelectric layer is measured by Fourier transform infrared spectroscopy, is less than 0.086. Here, the peak 1 has a strongest area intensity among peaks detected at wavenumbers of 475 cm?1 to 700 cm?1, and the peak 2 has an area intensity that is a sum of area intensities of peaks detected at wavenumbers of 1200 cm?1 to 1645 cm?1.Type: ApplicationFiled: October 2, 2023Publication date: April 4, 2024Inventors: Yoshiki YANO, Koji OHASHI, Yasuaki HAMADA, Kazuya KITADA
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Patent number: 11913684Abstract: A fluid circulation circuit includes a flow passage switching valve. The flow passage switching valve includes a body and a switcher. The body includes a first inlet, a second inlet, and outlets including a first outlet. The switcher is capable of switching a passage configuration to a state in which a fluid that has flowed in from the first inlet flows out of either one of the outlets and a state in which the fluid that has flowed in from the second inlet flows out of either one of the outlets.Type: GrantFiled: October 14, 2021Date of Patent: February 27, 2024Assignee: DENSO CORPORATIONInventors: Masamichi Makihara, Yoshiki Katoh, Takahiro Maeda, Kuniyoshi Tanioka, Akira Higuchi, Takehito Mizunuma, Takuya Hamada
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Patent number: 10957652Abstract: A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.Type: GrantFiled: February 13, 2020Date of Patent: March 23, 2021Assignee: TAIYO YUDENCO., LTD.Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
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Publication number: 20200185332Abstract: A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.Type: ApplicationFiled: February 13, 2020Publication date: June 11, 2020Applicant: TAIYO YUDEN CO., LTD.Inventors: Yuichi SUGIYAMA, Masashi MIYAZAKI, Yoshiki HAMADA
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Patent number: 10607940Abstract: A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.Type: GrantFiled: August 7, 2018Date of Patent: March 31, 2020Assignee: TAIYO YUDEN CO., LTD.Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
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Publication number: 20190051608Abstract: A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.Type: ApplicationFiled: August 7, 2018Publication date: February 14, 2019Applicant: TAIYO YUDEN CO., LTD.Inventors: Yuichi SUGIYAMA, Masashi MIYAZAKI, Yoshiki HAMADA
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Patent number: 9713259Abstract: A circuit substrate having a built-in component includes a core layer that is a conductive layer in which a penetrating hole is formed. A component is disposed in this penetrating hole. A signal wiring line that transmits high frequency signals is formed in a conductive layer facing the core layer on an area projected in the thickness direction of the penetrating hole. The component is provided with a ground conductor functioning as ground that is formed on at least a portion of the area projected in the thickness direction of the signal wiring line.Type: GrantFiled: October 10, 2014Date of Patent: July 18, 2017Assignee: TAIYO YUDEN CO., LTD.Inventors: Yoshiki Hamada, Hiroshi Nakamura
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Patent number: 9560743Abstract: A multilayer circuit substrate obtained by alternately stacking conductor layers and insulator layers. The conductor layers include a core layer having a greater thickness than any of the other conductor layers and located in an inner layer of the multilayer circuit substrate. A first conductor layer facing the core layer through an insulator layer has first signal wires that transmit high frequency signals, and through-holes are formed in the core layer along the first signal wires in a location facing the first signal wires.Type: GrantFiled: April 29, 2013Date of Patent: January 31, 2017Assignee: TAIYO YUDEN CO., LTD.Inventors: Yoshiki Hamada, Yuichi Sugiyama, Akihiro Hoshino
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Patent number: 9484372Abstract: A substrate for embedding an imaging device includes: a core layer; a first multilayered wiring layer that is formed onto the core layer, the core layer and the first multilayered wiring layer having a cavity penetrating therethrough; a second multilayered wiring layer that is formed onto the core layer on a side opposite to the first multilayered wiring layer and that includes a conductive pattern formed at a position facing the cavity; a resin portion that is arranged inside the cavity and includes a bottom surface supported by the second multilayered wiring layer, a side face supported by the core layer, and a curved surface formed on a side opposite to the bottom surface; and an imaging device adhered along the curved surface inside the cavity.Type: GrantFiled: December 4, 2015Date of Patent: November 1, 2016Assignee: TAIYO YUDEN CO., LTD.Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yoshiki Hamada
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Publication number: 20160163751Abstract: A substrate for embedding an imaging device includes: a core layer; a first multilayered wiring layer that is formed onto the core layer, the core layer and the first multilayered wiring layer having a cavity penetrating therethrough; a second multilayered wiring layer that is formed onto the core layer on a side opposite to the first multilayered wiring layer and that includes a conductive pattern formed at a position facing the cavity; a resin portion that is arranged inside the cavity and includes a bottom surface supported by the second multilayered wiring layer, a side face supported by the core layer, and a curved surface formed on a side opposite to the bottom surface; and an imaging device adhered along the curved surface inside the cavity.Type: ApplicationFiled: December 4, 2015Publication date: June 9, 2016Applicant: TAIYO YUDEN CO., LTD.Inventors: Yuichi SUGIYAMA, Masashi MIYAZAKI, Yoshiki HAMADA
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Publication number: 20150282328Abstract: A circuit substrate having a built-in component includes a core layer that is a conductive layer in which a penetrating hole is formed. A component is disposed in this penetrating hole. A signal wiring line that transmits high frequency signals is formed in a conductive layer facing the core layer on an area projected in the thickness direction of the penetrating hole. The component is provided with a ground conductor functioning as ground that is formed on at least a portion of the area projected in the thickness direction of the signal wiring line.Type: ApplicationFiled: October 10, 2014Publication date: October 1, 2015Applicant: TAIYO YUDEN CO., LTD.Inventors: Yoshiki HAMADA, Hiroshi NAKAMURA
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Patent number: 9078370Abstract: Provided is a substrate with a built-in electronic component that can minimize an occurrence of a deformation such as warping or distortion of the substrate with a built-in electronic component, which is caused by a difference in rigidity between a region of low rigidity and a region of high rigidity that are formed in a core layer thereof. In the substrate with a built-in electronic component, electronic components 12 are respectively housed in a plurality of housing portions 11a1 that are formed in a core layer 11a, and in the core layer 11a, a plurality of openings 11a2 filled with an insulator 11k are formed.Type: GrantFiled: August 20, 2012Date of Patent: July 7, 2015Assignee: TAIYO YUDEN CO., LTD.Inventors: Yuichi Sugiyama, Tatsuro Sawatari, Yusuke Inoue, Masashi Miyazaki, Yoshiki Hamada, Toshiyuki Kagawa
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Patent number: 8988885Abstract: An electronic circuit module includes a substrate with built-in component, a mount component mounted on the substrate with built-in component, a sealing portion covering the mount component, and a shield made of a conductive synthetic resin covering the sealing portion. The substrate with built-in component has a core layer made of a metal, an outer cover made of an insulating synthetic resin, and a first protrusion. The core layer has corners and side faces. The outer cover covers the corners and the side faces, and has a first surface. The first protrusion has a first end face exposed at the outer cover and a second surface adjacent to the first surface, and is formed away from the corners of the side faces to protrude outwardly. The sealing portion covers the mount component. The shield covers the sealing portion, and has a third surface bonded to the first surface and the second surface.Type: GrantFiled: November 6, 2013Date of Patent: March 24, 2015Assignee: Taiyo Yuden Co., LtdInventors: Tatsuro Sawatari, Masashi Miyazaki, Yoshiki Hamada, Yuichi Sugiyama, Kazuaki Ida
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Patent number: 8791783Abstract: An electronic component to be embedded in a substrate is configured so that planar coils protected by insulators are sandwiched be a pair of magnetic layers. Ports, or openings or absent parts are provided at predetermined positions of one or both of the magnetic layers, and the predetermined positions correspond to the positions opposite to terminal electrodes of the planar coils. Accordingly, a contribution to reduction of the size and weight of electronic equipment can be made.Type: GrantFiled: May 11, 2011Date of Patent: July 29, 2014Assignee: Taiyo Yuden Co., Ltd.Inventors: Masashi Miyazaki, Yuichi Sugiyama, Yoshiki Hamada, Yutaka Hata, Hideki Yokota
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Publication number: 20140144692Abstract: A multilayer circuit substrate obtained by alternately stacking conductor layers and insulator layers. The conductor layers include a core layer having a greater thickness than any of the other conductor layers and located in an inner layer of the multilayer circuit substrate. A first conductor layer facing the core layer through an insulator layer has first signal wires that transmit high frequency signals, and through-holes are formed in the core layer along the first signal wires in a location facing the first signal wires.Type: ApplicationFiled: April 29, 2013Publication date: May 29, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Yoshiki HAMADA, Yuichi SUGIYAMA, Akihiro HOSHINO
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Publication number: 20140126157Abstract: An electronic circuit module includes a substrate with built-in component, a mount component mounted on the substrate with built-in component, a sealing portion covering the mount component, and a shield made of a conductive synthetic resin covering the sealing portion. The substrate with built-in component has a core layer made of a metal, an outer cover made of an insulating synthetic resin, and a first protrusion. The core layer has corners and side faces. The outer cover covers the corners and the side faces, and has a first surface. The first protrusion has a first end face exposed at the outer cover and a second surface adjacent to the first surface, and is formed away from the corners of the side faces to protrude outwardly. The sealing portion covers the mount component. The shield covers the sealing portion, and has a third surface bonded to the first surface and the second surface.Type: ApplicationFiled: November 6, 2013Publication date: May 8, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Tatsuro SAWATARI, Masashi MIYAZAKI, Yoshiki HAMADA, Yuichi SUGIYAMA, Kazuaki IDA
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Publication number: 20140048321Abstract: Provided is a substrate with a built-in electronic component that can minimize an occurrence of a deformation such as warping or distortion of the substrate with a built-in electronic component, which is caused by a difference in rigidity between a region of low rigidity and a region of high rigidity that are formed in a core layer thereof. In the substrate with a built-in electronic component, electronic components 12 are respectively housed in a plurality of housing portions 11a1 that are formed in a core layer 11a, and in the core layer 11a, a plurality of openings 11a2 filled with an insulator 11k are formed.Type: ApplicationFiled: August 20, 2012Publication date: February 20, 2014Applicant: TAIYO YUDEN CO., LTD.Inventors: Yuichi Sugiyama, Tatsuro Sawatari, Yusuke Inoue, Masashi Miyazaki, Yoshiki Hamada, Toshiyuki Kagawa
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Publication number: 20130200977Abstract: An electronic component to be embedded in a substrate is configured so that planar coils protected by insulators are sandwiched be a pair of magnetic layers. Ports, or openings or absent parts are provided at predetermined positions of one or both of the magnetic layers, and the predetermined positions correspond to the positions opposite to terminal electrodes of the planar coils. Accordingly, a contribution to reduction of the size and weight of electronic equipment can be made.Type: ApplicationFiled: May 11, 2011Publication date: August 8, 2013Applicant: TAIYO YUDEN CO., LTD.Inventors: Masashi Miyazaki, Yuichi Sugiyama, Yoshiki Hamada, Yutaka Hata, Hideki Yokota
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Patent number: 4310682Abstract: A halo-salycylanilide of the following formula ##STR1## wherein R.sub.1 represents hydrogen or acyl group, R.sub.2 represents alkyl group, and both X.sub.1 and X.sub.2 represent halogen, has high antifungal and bactericidal activity.Type: GrantFiled: February 22, 1980Date of Patent: January 12, 1982Inventors: Isao Ozawa, Tomiyoshi Ito, Yoshiki Hamada, Isao Takeuchi