Abstract: Provided is a vehicle structure disposed at a lower portion of a center of a vehicle body, the vehicle structure including: a battery cover, a battery tray, and a structural member A for absorbing impact energy. Each of the battery cover and the battery tray is configured with an integrally molded fiber-reinforced plastic. The structural member A is located outside in a vehicle width direction of at least the battery cover and the battery tray. The structural member A is fastened together with the battery cover and the battery tray.

Abstract: A vehicle structure includes a battery tray disposed at a lower portion of a center of a vehicle body, and a cross member extending in a vehicle width direction and inserted into the battery tray. The battery tray includes a first bottom portion, a peripheral wall erected on an outer periphery of the first bottom portion, a first inner wall connected to the first bottom portion, a second inner wall connected to the first bottom portion, and a second bottom portion connected to both the first inner wall and the second inner wall and raised from the first bottom portion, which are configured with an integrally molded fiber-reinforced plastic. A recessed portion extending in the vehicle width direction is formed by the first inner wall, the second inner wall, and the second bottom portion. The cross member is inserted into at least one location of the recessed portion.

Abstract: A vehicle component includes a body, a first beam, and a second beam. The body has a first fixture region and a second fixture region. The first beam is formed of a first composite material and has a first beam shape. The first beam is attached to the body and extends between the first fixture region and the second fixture region of the body. The second beam is formed of a second composite material and has a second beam shape that is simple compared to the first beam shape. The second beam is attached to the body and extends between the first fixture region and the second fixture region of the body.

Abstract: A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.

Abstract: A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.

Abstract: A pulse detection device detects a pulse signal having an intermediate potential in a predefined period. Furthermore, the pulse detection device includes a signal fixing section that fixes the intermediate potential of the pulse signal at a low level or a high level. Furthermore, the signal fixing section is preferably a pull-down resistor or a pull-up resistor connected to an input signal line to which the pulse signal is input. Note that a pulse detection method may fix the intermediate potential of the pulse signal at a low level or a high level.

Abstract: A pulse detection device detects a pulse signal having an intermediate potential in a predefined period. Furthermore, the pulse detection device includes a signal fixing section that fixes the intermediate potential of the pulse signal at a low level or a high level. Furthermore, the signal fixing section is preferably a pull-down resistor or a pull-up resistor connected to an input signal line to which the pulse signal is input. Note that a pulse detection method may fix the intermediate potential of the pulse signal at a low level or a high level.

Abstract: In a method of verifying a delay time of a target circuit section, a first determination of a shortest of short delay times of each of components of the target circuit section in two or more temperature conditions is carried out. A second determination of a longest one of long delay times of each of the components of the target circuit section in two or more temperature conditions is carried out. Then, a first summation of the shortest delay times of the components is calculated and a second summation of the longest delay times of the components is calculated. Then, whether each of the first and second summations satisfy a predetermined timing constraint is verified.

Abstract: To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing shoot-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.

Abstract: In a method of verifying a delay time of a target circuit section, a first determination of a shortest of short delay times of each of components of the target circuit section in two or more temperature conditions is carried out. A second determination of a longest one of long delay times of each of the components of the target circuit section in two or more temperature conditions is carried out. Then, a first summation of the shortest delay times of the components is calculated and a second summation of the longest delay times of the components is calculated. Then, whether each of the first and second summations satisfy a predetermined timing constraint is verified.

Abstract: To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing short-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.