Patents by Inventor Yoshiki Makiuchi

Yoshiki Makiuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10895888
    Abstract: A watch is provided that includes a constant current circuit including: a plurality of transistors coupled in series between a first power supply and a second power supply, the first power supply being a power supply of a high potential side power supply, the second power supply being a power supply of a low potential side power supply; a plurality of connection wiring lines each provided for each of the plurality of transistors, and configured to couple the first power supply and a terminal on the first power supply side of each of the plurality of transistors; a non-disconnected fuse provided in a non-disconnected state to one connection wiring line of the plurality of connection wiring lines, and a disconnected fuse provided in a disconnected state to a connection wiring line other than the one connection wiring line of the plurality of connection wiring lines.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: January 19, 2021
    Inventor: Yoshiki Makiuchi
  • Publication number: 20200319663
    Abstract: A watch is provided that includes a constant current circuit including: a plurality of transistors coupled in series between a first power supply and a second power supply, the first power supply being a power supply of a high potential side power supply, the second power supply being a power supply of a low potential side power supply; a plurality of connection wiring lines each provided for each of the plurality of transistors, and configured to couple the first power supply and a terminal on the first power supply side of each of the plurality of transistors; a non-disconnected fuse provided in a non-disconnected state to one connection wiring line of the plurality of connection wiring lines, and a disconnected fuse provided in a disconnected state to a connection wiring line other than the one connection wiring line of the plurality of connection wiring lines.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Inventor: Yoshiki MAKIUCHI
  • Patent number: 10635126
    Abstract: In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yoshiki Makiuchi
  • Patent number: 10581379
    Abstract: An integrated circuit includes first and second coils, a first pad connected to the first coil and to a resonator, a second pad connected to the second coil and to the resonator, and first and second output terminals. The first pad is arranged to provide signals between the resonator and the first coil. The second pad is arranged to provide signals between the resonator and the second coil. A distance between the first pad and the first coil is less than a distance between the first coil and the first output terminal and a distance between the first coil and the second output terminal. A distance between the second pad and the second coil is less than a distance between the second coil and the first output terminal and a distance between the second coil and the second output terminal.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 3, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Masataka Nomura, Shigeki Sasayama, Akira Nakada, Yoshiki Makiuchi
  • Publication number: 20190302823
    Abstract: In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiki MAKIUCHI
  • Publication number: 20190296690
    Abstract: An integrated circuit includes first and second coils, a first pad connected to the first coil and to a resonator, a second pad connected to the second coil and to the resonator, and first and second output terminals. The first pad is arranged to provide signals between the resonator and the first coil. The second pad is arranged to provide signals between the resonator and the second coil. A distance between the first pad and the first coil is less than a distance between the first coil and the first output terminal and a distance between the first coil and the second output terminal. A distance between the second pad and the second coil is less than a distance between the second coil and the first output terminal and a distance between the second coil and the second output terminal.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Masataka NOMURA, Shigeki SASAYAMA, Akira NAKADA, Yoshiki MAKIUCHI
  • Patent number: 10361658
    Abstract: An oscillation module includes an oscillation circuit which includes a first coil and a second coil and a filter circuit which is provided at a stage subsequent to the oscillation circuit and includes a third coil. The first coil, the second coil, and the third coil are a part of an integrated circuit. The third coil is arranged so as to intersect a virtual straight line equidistant from the center of the first coil and the center of the second coil, in a plan view of the integrated circuit.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 23, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Masataka Nomura, Shigeki Sasayama, Akira Nakada, Yoshiki Makiuchi
  • Publication number: 20170117848
    Abstract: An oscillation module includes: an oscillation circuit which includes a first coil and a second coil; and a filter circuit which is provided at a stage subsequent to the oscillation circuit and includes a third coil, in which the first coil, the second coil, and third coil are a part of an integrated circuit, and the third coil is arranged so as to intersect a virtual straight line equidistant from the center of the first coil and the center of the second coil, in a plan view of the integrated circuit.
    Type: Application
    Filed: October 20, 2016
    Publication date: April 27, 2017
    Inventors: Masataka NOMURA, Shigeki SASAYAMA, Akira NAKADA, Yoshiki MAKIUCHI
  • Patent number: 9628020
    Abstract: A semiconductor circuit includes an oscillation circuit; an output circuit that receives a first oscillation signal from the oscillation circuit and outputs a second oscillation signal; a DC circuit that receives a voltage based on a power supply voltage and outputs at least one of a DC voltage and a DC current; and a semiconductor substrate on which the oscillation circuit, the output circuit, and the DC circuit are formed. In a plan view of the semiconductor substrate, the DC circuit is disposed between the oscillation circuit and the output circuit.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 18, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Kobayashi, Yoshiki Makiuchi, Takeshi Yasui
  • Publication number: 20160094182
    Abstract: A semiconductor circuit includes an oscillation circuit; an output circuit that receives a first oscillation signal from the oscillation circuit and outputs a second oscillation signal; a DC circuit that receives a voltage based on a power supply voltage and outputs at least one of a DC voltage and a DC current; and a semiconductor substrate on which the oscillation circuit, the output circuit, and the DC circuit are formed. In a plan view of the semiconductor substrate, the DC circuit is disposed between the oscillation circuit and the output circuit.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 31, 2016
    Inventors: Hitoshi Kobayashi, Yoshiki Makiuchi, Takeshi Yasui
  • Publication number: 20150145611
    Abstract: An oscillator circuit includes an oscillating amplifier circuit to which an oscillator element is connected, and which generates an oscillation signal, and a plurality of MOS type variable capacitance elements each having two terminals, one of which is electrically connected to the oscillating amplifier circuit, the MOS type variable capacitance elements have respective threshold voltages different from each other, a control voltage is applied to one of the terminals of each of the MOS type variable capacitance elements, and a reference voltage is applied to the other of the terminals of each of the MOS type variable capacitance elements. It is also possible for the MOS type variable capacitance elements to be different from each other in dope amount of impurities to a semiconductor layer below a gate electrode.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Hisahiro ITO, Yasunari FURUYA, Yoshiki MAKIUCHI, Hitoshi KOBAYASHI
  • Patent number: 6686792
    Abstract: A constant-voltage generation circuit 100 creates a constant voltage. This constant-voltage generation circuit 100 comprises a first voltage creation circuit 110 for creating a reference voltage and a second voltage creation circuit 130 for creating the constant voltage which has a predetermined relationship with the reference voltage. The first voltage creation circuit 110 comprises a first constant-current source 150-1 for supplying a constant current and a first voltage-control transistor 112, through which this constant current flows, for outputting the reference voltage on the basis of a predetermined potential. The constant current is set to a value within the saturated operating region of the first voltage control transistor 112.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: February 3, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Shinji Nakamiya, Tadao Kadowaki, Yoshiki Makiuchi
  • Patent number: 6593823
    Abstract: An oscillation circuit including a first electrostatic protection circuit connected between a signal path of the oscillation circuit and a constant-voltage side, and bypassing an electrostatic voltage of a first polarity that intrudes into the signal path to a side of a constant bypass voltage through a first semiconductor rectifier element. A second electrostatic protection circuit is connected between the signal path and a reference potential side, and bypassing an electrostatic voltage of a second polarity that intrudes into the signal path to the reference potential side through a second semiconductor rectifier element. The constant bypass voltage is set to a value such that the first and second semiconductor rectifier elements are not turned on by voltage change in the signal path caused by a leakage current, even when a leakage current is generated between the signal path and a power-supply voltage line.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: July 15, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Shinji Nakamiya, Hiroshi Yabe, Tadao Kadowaki, Yoshiki Makiuchi
  • Patent number: 6411169
    Abstract: This invention relates to a crystal oscillation circuit that oscillates stably with a low power consumption. This crystal oscillation circuit comprises an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The sum of the absolute value of the threshold voltage of a first semiconductor switching element and the absolute value of the threshold voltage of a second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, when said inverting amplifier includes the first and second semiconductor switching elements.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: June 25, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Yabe, Shinji Nakamiya, Tadao Kadowaki, Yoshiki Makiuchi
  • Publication number: 20020070792
    Abstract: A constant-voltage generation circuit 100 creates a constant voltage. This constant-voltage generation circuit 100 comprises a first voltage creation circuit 110 for creating a reference voltage and a second voltage creation circuit 130 for creating the constant voltage which has a predetermined relationship with the reference voltage. The first voltage creation circuit 110 comprises a first constant-current source 150-1 for supplying a constant current and a first voltage-control transistor 112, through which this constant current flows, for outputting the reference voltage on the basis of a predetermined potential. The constant current is set to a value within the saturated operating region of the first voltage control transistor 112.
    Type: Application
    Filed: February 4, 2002
    Publication date: June 13, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Shinji Nakamiya, Tadao Kadowaki, Yoshiki Makiuchi
  • Publication number: 20020070817
    Abstract: There is provided an oscillation circuit that enables oscillation at a stable frequency, unaffected by changes in the power-supply voltage of a main power source.
    Type: Application
    Filed: September 26, 2001
    Publication date: June 13, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shinji Nakamiya, Hiroshi Yabe, Tadao Kadowaki, Yoshiki Makiuchi
  • Publication number: 20010052809
    Abstract: A constant-voltage generation circuit 100 creates a constant voltage.
    Type: Application
    Filed: August 6, 2001
    Publication date: December 20, 2001
    Applicant: Seiko Epson Corporation
    Inventors: Tadao Kadowaki, Yoshiki Makiuchi, Shinji Nakamiya
  • Publication number: 20010043106
    Abstract: A constant-voltage generation circuit 100 creates a constant voltage.
    Type: Application
    Filed: June 29, 2001
    Publication date: November 22, 2001
    Applicant: Seiko Epson Corporation
    Inventors: Tadao Kadowaki, Yoshiki Makiuchi, Shinji Nakamiya
  • Patent number: 6288600
    Abstract: A constant-voltage generation circuit is provided which creates a constant voltage. The constant-voltage generation circuit may consist of a first voltage creation circuit for creating a reference voltage and a second voltage creation circuit for creating a constant voltage which has a predetermined relationship with the reference voltage. The first voltage creation circuit may consist of a constant-current source for supplying a constant current and a voltage-control transistor through which this constant current flows, for outputting the reference voltage on the basis of a predetermined potential. The constant current is set to a value within the saturated operating region of the voltage-control transistor.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: September 11, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Tadao Kadowaki, Yoshiki Makiuchi, Shinji Nakamiya
  • Patent number: RE39329
    Abstract: This invention relates to a crystal oscillation circuit that oscillates stably with a low power consumption. This crystal oscillation circuit comprises an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The sum of the absolute value of the threshold voltage of a first semiconductor switching element and the absolute value of the threshold voltage of a second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, when said inverting amplifier includes the first and second semiconductor switching elements.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: October 10, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Yabe, Shinji Nakamiya, Tadao Kadowaki, Yoshiki Makiuchi