Patents by Inventor Yoshiki Nakatani
Yoshiki Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8623681Abstract: An auxiliary capacitor (6a) includes a capacitor line (11ba), a gate insulating film (12) provided so as to cover the capacitor line (11ba), a semiconductor layer (13b) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b), and a drain electrode (14ba) provided on the semiconductor layer (13b) and connected to a pixel electrode (16a). The semiconductor layer (13b) made of an oxide semiconductor and the pixel electrode (16a) made of an oxide conductor contact each other.Type: GrantFiled: July 1, 2011Date of Patent: January 7, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshiki Nakatani, Yuhichi Saitoh, Tetsuya Okamoto, Yohsuke Kanzaki, Yudai Takanishi
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Patent number: 8605028Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.Type: GrantFiled: June 16, 2009Date of Patent: December 10, 2013Assignee: Sharp Kabushiki KaishaInventors: Mayuko Sakamoto, Yasuaki Iwase, Yoshiki Nakatani, Yoshihisa Takahashi
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Patent number: 8558232Abstract: The present invention aims at reducing an OFF current in a thin film transistor while maintaining an ON-state current. A TFT (100) includes a glass substrate (101) formed thereon with a source electrode (110) and a drain electrode (112) having their respective upper surfaces formed with n-type silicon layers (120, 121) of microcrystalline silicon. Microcrystalline silicon regions (135, 136) are formed respectively on the n-type silicon layers (120, 121) while an amorphous silicon region (130) is formed on the glass substrate (101), and these are covered by a microcrystalline silicon layer (145). Therefore, ON-state current flows from the drain electrode (112), through the microcrystalline silicon region (135), the microcrystalline silicon layer (145) and the microcrystalline silicon region (136) in this order, and then to the source electrode (110). Also, OFF current is limited by the amorphous silicon region (130).Type: GrantFiled: April 21, 2010Date of Patent: October 15, 2013Assignee: Sharp Kabushiki KaishaInventors: Yoshiki Nakatani, Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi
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Publication number: 20130214272Abstract: An auxiliary capacitor (6a) includes a capacitor line (11ba), a gate insulating film (12) provided so as to cover the capacitor line (11ba), a semiconductor layer (13b) provided on the gate insulating film (12) so as to overlap with the capacitor line (11b), and a drain electrode (14ba) provided on the semiconductor layer (13b) and connected to a pixel electrode (16a). The semiconductor layer (13b) made of an oxide semiconductor and the pixel electrode (16a) made of an oxide conductor contact each other.Type: ApplicationFiled: July 1, 2011Publication date: August 22, 2013Applicant: Sharp Kabushiki KaishaInventors: Yoshiki Nakatani, Yuhichi Saitoh, Tetsuya Okamoto, Yohsuke Kanzaki, Yudai Takanishi
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Publication number: 20130215370Abstract: A thin film transistor substrate (20) includes: an insulating substrate (10a); a gate insulating layer (12) provided on the insulating substrate (10a); a connection layer (25) provided on the gate insulating layer (12), and made of indium gallium zinc oxide (IGZO); a drain electrode (16b) provided on the connection layer (25), and made of titanium; a contact hole (Ca) formed in the connection layer (25) and the drain electrode (16b); and a pixel electrode (19a) provided on a surface of the contact hole (Ca), and contacting the connection layer (25). The drain electrode (16b) and the pixel electrode (19a) are electrically connected together through the connection layer (25).Type: ApplicationFiled: May 11, 2011Publication date: August 22, 2013Applicant: Sharp Kabushiki KaishaInventors: Yudai Takanishi, Yohsuke Kanzaki, Tetsuya Okamoto, Yuhichi Saitoh, Yoshiki Nakatani
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Publication number: 20130208207Abstract: An active matrix substrate (20) includes: a gate electrode (11) provided on an insulating substrate (10a); a gate insulating layer (12) covering the gate electrode (11); an oxide semiconductor layer (13) provided on the gate insulating layer (12); and a protective layer (17) covering the oxide semiconductor layer (13). The active matrix substrate (20) has a display region (D) where an image is displayed and a gate terminal region (Ts) located around the display region (D) and including a gate terminal (26) for connection to an external circuit. The gate terminal (26) includes a terminal line (21) provided on the insulating substrate (10a). The terminal line (26) is made of a conductive material different from a material constituting the oxide semiconductor layer (13).Type: ApplicationFiled: May 24, 2011Publication date: August 15, 2013Applicant: Sharp Kabushiki KaishaInventors: Tetsuya Okamoto, Yoshiki Nakatani, Yudai Takanishi, Yohsuke Kanzaki, Yuhichi Saitoh
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Publication number: 20130175521Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.Type: ApplicationFiled: May 23, 2011Publication date: July 11, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi
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Patent number: 8316907Abstract: Substrate material processing equipment includes: a substrate material conveying section receiving a substrate material from a first line and conveying it to a second line; a first substrate material dividing section dividing the substrate material; a substrate material recovery section recovering the substrate material from its start edge formed by division; a substrate material supply section supplying a substrate material to an end edge of the substrate material which is formed by division; a first substrate material joining section joining the end edge of the substrate material to a start edge of the substrate material supplied from the substrate material supply section; a second substrate material dividing section provided between the substrate material supply section and the first substrate material joining section; a third substrate material dividing section provided between the first line and the substrate material recovery section; and a second substrate material joining section joining a start edgeType: GrantFiled: November 13, 2007Date of Patent: November 27, 2012Assignee: Sharp Kabushiki KaishaInventors: Akitsugu Hatano, Yoshiki Nakatani, Hisao Ochi
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Publication number: 20120223316Abstract: Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer 60 of the TFT 10 is formed of a crystalline silicon, and the lower surface of one end of the channel layer 60 is electrically connected to the surface of an n+ silicon layer 40a, and the lower surface of the other end is electrically connected to the surface of an n+ silicon layer 40b. Furthermore, the side surface of said end of the channel layer 60 is electrically connected to a source electrode 50a, and the side surface of the other end is electrically connected to a drain electrode 50b. Thus, a barrier that makes electrons, which act as carriers, not easily transferred is formed on the boundary between the source electrode 50a and the channel layer 60. As a result, the ON current that flows when the TFT 10 is in the ON state can be increased, and the leak current that flows when the TFT is in the OFF state can be reduced.Type: ApplicationFiled: July 8, 2010Publication date: September 6, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yohsuke Kanzaki, Yudai Takanishi, Yoshiki Nakatani
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Publication number: 20120138931Abstract: The present invention aims at reducing an OFF current in a thin film transistor while maintaining an ON-state current. A TFT (100) includes a glass substrate (101) formed thereon with a source electrode (110) and a drain electrode (112) having their respective upper surfaces formed with n-type silicon layers (120, 121) of microcrystalline silicon. Microcrystalline silicon regions (135, 136) are formed respectively on the n-type silicon layers (120, 121) while an amorphous silicon region (130) is formed on the glass substrate (101), and these are covered by a microcrystalline silicon layer (145). Therefore, ON-state current flows from the drain electrode (112), through the microcrystalline silicon region (135), the microcrystalline silicon layer (145) and the microcrystalline silicon region (136) in this order, and then to the source electrode (110). Also, OFF current is limited by the amorphous silicon region (130).Type: ApplicationFiled: April 21, 2010Publication date: June 7, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshiki Nakatani, Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi
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Publication number: 20110193853Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.Type: ApplicationFiled: June 16, 2009Publication date: August 11, 2011Applicant: Sharp Kabushiki KaishaInventors: Mayuko Sakamoto, Yasuaki Iwase, Yoshiki Nakatani, Yoshihisa Takahashi
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Publication number: 20100065191Abstract: Substrate material processing equipment includes: a substrate material conveying section receiving a substrate material from a first line and conveying it to a second line; a first substrate material dividing section dividing the substrate material; a substrate material recovery section recovering the substrate material from its start edge formed by division; a substrate material supply section supplying a substrate material to an end edge of the substrate material which is formed by division; a first substrate material joining section joining the end edge of the substrate material to a start edge of the substrate material supplied from the substrate material supply section; a second substrate material dividing section provided between the substrate material supply section and the first substrate material joining section; a third substrate material dividing section provided between the first line and the substrate material recovery section; and a second substrate material joining section joining a start edgeType: ApplicationFiled: November 13, 2007Publication date: March 18, 2010Applicant: SHARP KABUSHIKI KAISHAInventors: Akitsugu Hatano, Yoshiki Nakatani, Hisao Ochi
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Publication number: 20100051330Abstract: A wiring board formed by mounting an IC chip on a mounting substrate includes a resin substrate and a wiring pattern. The resin substrate includes having a reinforcing material obtained by impregnating glass fibers with a resin and an organic layer provided on a surface of the reinforcing material. The wiring pattern is disposed on a surface of the resin substrate through a coating layer. The IC chip includes a bump electrode for connection with the wiring pattern. The resin substrate includes a fiber exposure portion through which the reinforcing material is exposed, and the IC chip is fixed to the mounting substrate through an ACF adhered to the fiber exposure portion with the connection electrode being connected to the wiring pattern.Type: ApplicationFiled: July 18, 2007Publication date: March 4, 2010Applicant: SHARP KABUSHIKI KAISHAInventors: Kenichi Yamashita, Yoshiki Nakatani, Akitsugu Hatano
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Publication number: 20090039495Abstract: An active matrix substrate includes a first substrate and a driving integrated circuit chip mounted on the first substrate. A support member is provided between the active matrix substrate and the driving IC chip so as to be in contact with both the active matrix substrate and the driving IC chip.Type: ApplicationFiled: June 13, 2006Publication date: February 12, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Kenichi Yamashita, Yoshiki Nakatani, Tetsuya Aita
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Patent number: 7431158Abstract: A flexible substrate storage equipment of the present invention includes at least a pair of opposed members that constitute an outer frame of a storage equipment main body, wherein the pair of opposed members are disposed so as to maintain a predetermined interval to wedge a plurality of flexible substrates in between to hold them in a shape of a curve. As a result, a flexible substrate storage equipment for surely storing and holding a plastic substrate or other flexible substrate with a simple structure, and a storing method of such substrate can be realized.Type: GrantFiled: February 18, 2004Date of Patent: October 7, 2008Assignee: Sharp Kabushiki KaishaInventors: Kimihiko Yamada, Yoshiki Nakatani, Tetsuya Aita
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Patent number: 6876407Abstract: A thin film two-terminal element is formed by laminating a protruding portion of a second conductor layer on a first conductor layer via a nonlinear resistor layer. An insulator layer is positioned between the first conductor layer and the second conductor layer except a region to become the thin film two-terminal element. Therefore, the allowance of the relative position of the second conductor layer with respect to the first conductor layer and the nonlinear resistor layer is considerably large as compared with that of prior art, and it is possible to ensure a requisite alignment margin with respect to deformation of the substrate in the production process.Type: GrantFiled: March 28, 2003Date of Patent: April 5, 2005Assignee: Sharp Kabushiki KaishaInventors: Yoshiki Nakatani, Shigeru Aomori, Tomoko Maruyama
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Publication number: 20040163988Abstract: A flexible substrate storage equipment of the present invention includes at least a pair of opposed members that constitute an outer frame of a storage equipment main body, wherein the pair of opposed members are disposed so as to maintain a predetermined interval to wedge a plurality of flexible substrates in between to hold them in a shape of a curve. As a result, a flexible substrate storage equipment for surely storing and holding a plastic substrate or other flexible substrate with a simple structure, and a storing method of such substrate can be realized.Type: ApplicationFiled: February 18, 2004Publication date: August 26, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Kimihiko Yamada, Yoshiki Nakatani, Tetsuya Aita
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Publication number: 20030227587Abstract: A thin film two-terminal element is formed by laminating a protruding portion of a second conductor layer on a first conductor layer via a nonlinear resistor layer. An insulator layer is positioned between the first conductor layer and the second conductor layer except a region to become the thin film two-terminal element. Therefore, the allowance of the relative position of the second conductor layer with respect to the first conductor layer and the nonlinear resistor layer is considerably large as compared with that of prior art, and it is possible to ensure a requisite alignment margin with respect to deformation of the substrate in the production process.Type: ApplicationFiled: March 28, 2003Publication date: December 11, 2003Inventors: Yoshiki Nakatani, Shigeru Aomori, Tomoko Maruyama
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Patent number: 6350557Abstract: A thin-film two-terminal element including first metal film functioning as a wiring layer and a first electrode, a first insulating film formed on the first electrode of the first metal film and having a non-linear resistance property, a second metal film formed on the first insulating film and functioning as a second electrode, and a third metal film formed in a wire layer portion of the first metal film and having a smaller stress and a smaller electrical resistance than the first metal film, and a thin-film two-terminal element including, on a resinous substrate as an insulative substrate, a first metal film functioning as a wiring layer and a first electrode, a first insulating film formed on the first electrode of the first metal film and having a non-linear resistance property, a second metal film formed on the first insulating film and functioning as a second electrode, and a second insulating film formed under the second metal film except on a portion thereof which electrically functions with the firsType: GrantFiled: January 31, 2000Date of Patent: February 26, 2002Assignee: Sharp Kabushiki KaishaInventors: Shigeru Aomori, Yoshiki Nakatani
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Patent number: 6069674Abstract: The liquid crystal display apparatus of the invention includes a device-formed substrate, a counter substrate, and a liquid crystal layer interposed therebetween. The device-formed substrate includes: a plurality of display electrodes for applying display voltages to the liquid crystal layer; a plurality of active devices for supplying the display voltages to the plurality of display electrodes, respectively; and image inputting devices for inputting an image. In the liquid crystal display apparatus, image processing means is provided for processing the image input by the image inputting devices.Type: GrantFiled: May 17, 1996Date of Patent: May 30, 2000Assignee: Sharp Kabushiki KaishaInventors: Shigeru Aomori, Yoshiki Nakatani