Patents by Inventor Yoshiki Niki
Yoshiki Niki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927490Abstract: A sticking-type deep body thermometer that includes a thermometer body; a sticking member having an adhesive property on a bottom surface of thermometer body; a first thermal resistor having a predetermined thermal resistance and disposed substantially parallel to the sticking member; a first temperature sensor configured to detect a first temperature at a first surface of the first thermal resistor adjacent to the sticking member; a second temperature sensor configured to detect a second temperature at a second surface of the first thermal resistor opposite the first surface; a deep body temperature detection circuit configured to estimate a deep body temperature based on the first temperature and the second temperature; and an attachment/detachment sensor configured to detect attachment and detachment of the sticking-type deep body thermometer in accordance with a temperature difference between the first temperature and the second temperature and/or a temperature rate of change of the first temperature.Type: GrantFiled: November 5, 2020Date of Patent: March 12, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshiki Niki, Toru Shimuta
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Patent number: 11828661Abstract: A core body thermometer is provided that includes a plate-shaped wiring substrate having a first region and a second region having different thermal resistances, a first temperature sensor and a second temperature sensor located in a first region and across a thickness direction of the first region and a third temperature sensor and a fourth temperature sensor located in a second region and across a thickness direction of the second region. Moreover, a processing circuit is provided that processes output signals of the first, second, third and fourth temperature sensors. The first and second regions are adjusted to have the different thermal resistances by varying occupancy and/or dispersion of the conductive patterns.Type: GrantFiled: July 15, 2020Date of Patent: November 28, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshiki Niki, Toru Shimuta
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Publication number: 20230229885Abstract: A method for reading an identification tag is provided that includes detecting a content of particles having a first feature amount as a specific feature amount, where the particles are included in the identification tag; and distinguishing a type of the identification tag by information on the content of the particles having the first feature amount.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Inventor: Yoshiki NIKI
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Publication number: 20210055168Abstract: A sticking-type deep body thermometer that includes a thermometer body; a sticking member having an adhesive property on a bottom surface of thermometer body; a first thermal resistor having a predetermined thermal resistance and disposed substantially parallel to the sticking member; a first temperature sensor configured to detect a first temperature at a first surface of the first thermal resistor adjacent to the sticking member; a second temperature sensor configured to detect a second temperature at a second surface of the first thermal resistor opposite the first surface; a deep body temperature detection circuit configured to estimate a deep body temperature based on the first temperature and the second temperature; and an attachment/detachment sensor configured to detect attachment and detachment of the sticking-type deep body thermometer in accordance with a temperature difference between the first temperature and the second temperature and/or a temperature rate of change of the first temperature.Type: ApplicationFiled: November 5, 2020Publication date: February 25, 2021Inventors: Yoshiki Niki, Toru Shimuta
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Publication number: 20200340865Abstract: A core body thermometer is provided that includes a plate-shaped wiring substrate having a first region and a second region having different thermal resistances, a first temperature sensor and a second temperature sensor arranged so as to interpose the first region from the thickness direction of the first region and a third temperature sensor and a fourth temperature sensor arranged so as to interpose the second region from the thickness direction of the second region. Moreover, a processing circuit is provided that processes output signals of the first, second, third and fourth temperature sensors. The first and second regions are adjusted to have the different thermal resistances by varying occupancy and/or dispersion of the conductive patterns.Type: ApplicationFiled: July 15, 2020Publication date: October 29, 2020Inventors: Yoshiki Niki, Toru Shimuta
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Patent number: 7622993Abstract: A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.Type: GrantFiled: August 8, 2008Date of Patent: November 24, 2009Assignee: Semiconductor Technology Academic Research CenterInventors: Yoshiki Niki, Haruo Kobayashi, Koichiro Mashiko
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Publication number: 20080297203Abstract: A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.Type: ApplicationFiled: August 8, 2008Publication date: December 4, 2008Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Yoshiki Niki, Haruo Kobayashi, Koichiro Mashiko
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Patent number: 7425870Abstract: There is disclosed a current mirror circuit comprising a first transistor having a first electrode connected to a first potential, a second electrode connected to a second potential lower than the first potential, and a third electrode connected to a third potential higher than the second potential, a second transistor having a first electrode connected to the first potential and the first electrode of the first transistor, and a second electrode connected to the second potential, an operational amplifier having a high-potential input connected to the third potential and the third electrode of the first transistor, and a low-potential input connected to the third electrode of the second transistor, and a third transistor having a first electrode connected to an output of the operational amplifier, a second electrode connected to the low-potential input and the third electrode of the second transistor, and a third electrode used as an output terminal.Type: GrantFiled: March 8, 2006Date of Patent: September 16, 2008Assignee: Semiconductor Technology Academic Research CenterInventors: Yoshiki Niki, Haruo Kobayashi, Koichiro Mashiko
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Publication number: 20060202763Abstract: There is disclosed a current mirror circuit comprising a first transistor having a first electrode connected to a first potential, a second electrode connected to a second potential lower than the first potential, and a third electrode connected to a third potential higher than the second potential, a second transistor having a first electrode connected to the first potential and the first electrode of the first transistor, and a second electrode connected to the second potential, an operational amplifier having a high-potential input connected to the third potential and the third electrode of the first transistor, and a low-potential input connected to the third electrode of the second transistor, and a third transistor having a first electrode connected to an output of the operational amplifier, a second electrode connected to the low-potential input and the third electrode of the second transistor, and a third electrode used as an output terminal.Type: ApplicationFiled: March 8, 2006Publication date: September 14, 2006Applicant: Semiconductor Technology Academic Research CenterInventors: Yoshiki Niki, Haruo Kobayashi, Koichiro Mashiko