Patents by Inventor Yoshiki Saito
Yoshiki Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240421259Abstract: A light emitting device includes: a flip-chip type light emitting element; a sealing portion; and a lens as defined herein, the light emitting element includes an n-type layer, an active layer, an electron blocking layer, a composition gradient layer, a p-type contact layer, and a p-side electrode as defined herein, and a thickness of the composition gradient layer is set such that light directed from the active layer toward the n-type layer and light directed from the active layer toward a side opposite to the n-type layer and then reflected by the p-side electrode toward the n-type layer strengthen each other in a direction perpendicular to a main surface of the light emitting element due to interference.Type: ApplicationFiled: June 13, 2024Publication date: December 19, 2024Inventors: Koji OKUNO, Yoshiki SAITO, Masaki OYA, Kengo NAGATA, Tetsuya TAKEUCHI, Satoshi KAMIYAMA, Motoaki IWAYA, Hisanori ISHIGURO, Rie IWATSUKI
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Patent number: 12127553Abstract: A cell cryopreservation method including adding a 1 volume % of a composition comprising 0.01 wt % to 20 wt % of a sophorose lipid to cells in a cell culture medium just before or up to 6 hours before cryopreserving the cells; and cryopreserving the cell culture medium, wherein the composition improves cell viability after cryopreservation compared to cells that are cryopreserved with a similar composition that does not contain the sophorose lipid.Type: GrantFiled: May 19, 2022Date of Patent: October 29, 2024Assignees: SARAYA CO., LTD., OSAKA UNIVERSITYInventors: Asuka Nogami, Motoki Tatsumi, Nanase Ishii, Mizuyuki Ryu, Yoshihiko Hirata, Yoshiki Sawa, Shigeru Miyagawa, Atsuhiro Saito, Hirotatsu Ohkawara
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Publication number: 20240335480Abstract: An object of the present invention is to provide a pericyte-like cell having high angiogenic potential with a higher cell proliferation ability than a primary pericyte available in the past and high VEGF expression, and a method for producing the same. Provided are a method for producing a VEGF-highly expressing pericyte-like cell, the method including selecting a CD56(?) pericyte-like cell from a population including a pericyte-like cell obtained by inducing differentiation of a pluripotent stem cell; and a VEGF-highly expressing pericyte-like cell produced by the production method.Type: ApplicationFiled: July 14, 2022Publication date: October 10, 2024Applicants: Astellas Pharma Inc., OSAKA UNIVERSITY, National Center for Child Health and DevelopmentInventors: Kenichiro SHIMATANI, Hiromu SATO, Masao SASAI, Yoshiki SAWA, Atsuhiro SAITO, Shigeru MIYAGAWA
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Publication number: 20240328648Abstract: A ventilation system includes a refrigerant circuit, supply and exhaust fans, and a control unit. The refrigerant circuit has a compressor and first and second heat exchangers connected by a refrigerant pipe with a refrigerant flowing in the refrigerant circuit. The supply fan is arranged to supply air from an outdoor space to an indoor space through the first heat exchanger. The exhaust fan is arranged to exhaust air in the indoor space to the outdoor space through the second heat exchanger. The control unit determines whether the supply fan and the exhaust fan are normal. The control unit, upon determining that one of the supply fan or the exhaust fan is abnormal, stops the one of the supply fan or the exhaust fan determined to be abnormal, and continues an operation of an other one of the supply fan or the exhaust fan determined to be normal.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: Takeru MIYAZAKI, Yoshiki YAMANOI, Yuta IYOSHI, Kumiko SAEKI, Masashi SAITO
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METHOD FOR PRODUCING VASCULAR ENDOTHELIAL GROWTH FACTOR (VEGF)- HIGHLY EXPRESSING PERICYTE-LIKE CELL
Publication number: 20240316115Abstract: An object of the present invention is to provide a pericyte-like cell having high angiogenic potential with a higher cell proliferation ability than a primary pericyte available in the past and high VEGF expression, and a method for producing the same. Provided are a method for producing a VEGF-highly expressing pericyte-like cell, the method including selecting a CD56(?) pericyte-like cell from a population including a pericyte-like cell obtained by inducing differentiation of a pluripotent stem cell; and a VEGF-highly expressing pericyte-like cell produced by the production method.Type: ApplicationFiled: July 14, 2022Publication date: September 26, 2024Applicants: Astellas Pharma Inc., OSAKA UNIVERSITYInventors: Kenichiro SHIMATANI, Hiromu SATO, Masao SASAI, Yoshiki SAWA, Atsuhiro SAITO, Shigeru MIYAGAWA -
Publication number: 20240311232Abstract: A memory system includes a nonvolatile memory including a memory cell, and a controller. The controller is configured to write multi-bit data into the memory cell through a first write operation of writing a first part, and not a second part, of the multi-bit data and then a second write operation of writing the first and second parts. The controller is configured to, during writing of the multi-bit data, determine an amount of time that has passed since the first write operation, perform the second write operation in a first manner by inputting the second part, and not the first part, from the controller, when the determined amount is less than a threshold amount, and perform the second write operation in a second manner by inputting the first and second parts from the controller, when the determined amount is greater than the threshold amount.Type: ApplicationFiled: February 22, 2024Publication date: September 19, 2024Inventors: Yuko NODA, Kiwamu WATANABE, Masahiro SAITO, Yoshiki TAKAI
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OPTICAL DETECTION DEVICE, MANUFACTURING METHOD OF OPTICAL DETECTION DEVICE, AND ELECTRONIC APPARATUS
Publication number: 20240290813Abstract: An optical detection device including a through electrode is provided. The optical detection device includes a first semiconductor layer having a photoelectric conversion region, a first surface, and a second surface that is a light entrance surface, a second semiconductor layer with a third surface and a fourth surface, a second wiring layer overlapped with the third surface, a third wiring layer overlapped with the fourth surface, a first wiring layer with one surface overlapped with the first surface and another surface overlapped with one of the second wiring layer and the third wiring layer, a first conductor that has a first width, includes a first material, and penetrates the second semiconductor layer in a thickness direction, and a second conductor that has a second width smaller than the first width, includes a second material different from the first material, and penetrates the second semiconductor layer in the thickness direction.Type: ApplicationFiled: June 16, 2022Publication date: August 29, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Masaki HANEDA, Kengo KOTOO, Yoshiki SHIRASU, Kazuki SHIMOMURA, Nobutoshi FUJII, Takaaki HIRANO, Yosuke FUJII, Takashi OINOUE, Suguru SAITO, Toshiyuki ISHIMARU, Keiji OHSHIMA, Shinichi IMAI, Takuya KUROTORI, Tomohiro SUGIYAMA, Ikue MITSUHASHI, Kenichi TOKUOKA -
Publication number: 20240078174Abstract: An information storage device includes a storage unit, a control unit, an allocation information storage unit, a QoS parameter storage unit, and a monitoring result storage unit. The control unit creates and manages a logical storage area using the storage area of the storage unit when a storage area allocation request is received. The allocation information storage unit stores allocation information related to logical storage areas. The QoS parameter storage unit stores quality requests expected to be satisfied for a communication for using the logical storage area. The control unit monitors the operating state and characteristics of the storage unit and the communication status, and stores the results in the monitoring result storage unit. The control unit derives internal QoS parameters to be set in the information storage device from the information stored in the allocation information storage unit, the QoS parameter storage unit, and the monitoring result storage unit.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Inventors: Takeshi ISHIHARA, Yohei HASEGAWA, Kenta YASUFUKU, Shohei ONISHI, Yoshiki SAITO, Junpei KIDA
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Patent number: 11916164Abstract: A method for manufacturing a light-emitting element includes providing the light-emitting element that includes a light-emitting layer with an emission wavelength of not more than 306 nm and a p-type layer including AlGaInN including Mg as an acceptor, and removing hydrogen in the p-type layer from the light-emitting element by irradiating the light-emitting element with ultraviolet light at a wavelength of not more than 306 nm from outside and treating the light-emitting element with heat in a state in which a reverse voltage, or a forward voltage lower than a threshold voltage of the light-emitting element, or no voltage is applied to the light-emitting element. The removing of hydrogen in the p-type layer from the light-emitting element is performed in a N2 atmosphere at not less than 650° C. or in a N2+O2 atmosphere at not less than 500° C.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignees: TOYODA GOSEI CO., LTD., MEIJO UNIVERSITYInventors: Yoshiki Saito, Shinya Boyama, Shinichi Matsui, Hiroshi Miwa, Kengo Nagata, Tetsuya Takeuchi, Hisanori Ishiguro
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Publication number: 20230395617Abstract: There is provided a solid-state imaging device capable of preventing the sensitivity difference from being generated between the pixels. The fixed imaging device of the present disclosure includes: a first pixel; and a second pixel located in a first direction of the first pixel, in which each of the first and second pixels includes a first transistor and a second transistor, and the first and second transistors in the second pixel are disposed periodically in the first direction with respect to the first and second transistors in the first pixel.Type: ApplicationFiled: October 19, 2021Publication date: December 7, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Mikinori ITO, Natsuko OOTANI, Yutaro KOMURO, Akira OKADA, Yuhei AOTANI, Yuichi YAMAGUCHI, Tsubasa SAKAKI, Masumi ABE, Kodai KANEYASU, Yuta NOGUCHI, Kazuki TAKAHASHI, Hirofumi YAMADA, Kohei YAMASHINA, Ryosuke TAKAHASHI, Yoshiki SAITO, Yusuke KIKUCHI, Yukihito IIDA, Kenichi OBATA, Ryuichi ITOH, Yuki UEMURA
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Patent number: 11836039Abstract: According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.Type: GrantFiled: September 3, 2021Date of Patent: December 5, 2023Assignee: Kioxia CorporationInventor: Yoshiki Saito
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Patent number: 11726712Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes first and second memory areas. The controller is configured to, when receiving a write command from the host, determine a write method. The controller is configured to, when a first method is determined, write the data to the first memory area. The controller is configured to, when a second method is determined, write the data to the second memory area. The first method is a write method of writing the data to a physical address associated with the logical address designated in the write command. The second method is a write method of writing the data to a physical address designated by the controller.Type: GrantFiled: June 10, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventor: Yoshiki Saito
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Publication number: 20220308953Abstract: According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.Type: ApplicationFiled: September 3, 2021Publication date: September 29, 2022Inventor: Yoshiki Saito
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Publication number: 20220231189Abstract: A method for manufacturing a light-emitting element includes providing the light-emitting element that includes a light-emitting layer with an emission wavelength of not more than 306 nm and a p-type layer including AlGaInN including Mg as an acceptor, and removing hydrogen in the p-type layer from the light-emitting element by irradiating the light-emitting element with ultraviolet light at a wavelength of not more than 306 nm from outside and treating the light-emitting element with heat in a state in which a reverse voltage, or a forward voltage lower than a threshold voltage of the light-emitting element, or no voltage is applied to the light-emitting element. The removing of hydrogen in the p-type layer from the light-emitting element is performed in a N2 atmosphere at not less than 650° C. or in a N2+O2 atmosphere at not less than 500° C.Type: ApplicationFiled: December 29, 2021Publication date: July 21, 2022Inventors: Yoshiki Saito, Shinya Boyama, Shinichi Matsui, Hiroshi Miwa, Kengo Nagata, Tetsuya Takeuchi, Hisanori Ishiguro
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Publication number: 20220190202Abstract: A light-emitting element includes an n-type contact layer which includes AlGaN and in which a Fermi level and a conduction band are in degeneracy, and a light-emitting layer including AlGaN and being stacked on the n-type contact layer. An Al composition x of the n-type contact layer is not less than 0.1 greater than an Al composition x of the light-emitting layer. The n-type contact layer has an effective donor concentration that is a concentration to cause the degeneracy and that is not more than 4.0×1019 cm?3.Type: ApplicationFiled: November 18, 2021Publication date: June 16, 2022Inventors: Kengo NAGATA, Yoshiki SAITO, Keita KATAOKA, Tetsuo NARITA, Kayo KONDO
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Publication number: 20220083273Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes first and second memory areas. The controller is configured to, when receiving a write command from the host, determine a write method. The controller is configured to, when a first method is determined, write the data to the first memory area. The controller is configured to, when a second method is determined, write the data to the second memory area. The first method is a write method of writing the data to a physical address associated with the logical address designated in the write command. The second method is a write method of writing the data to a physical address designated by the controller.Type: ApplicationFiled: June 10, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventor: Yoshiki SAITO
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Patent number: 10922240Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.Type: GrantFiled: March 11, 2019Date of Patent: February 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Onishi, Yoshiki Saito, Yohei Hasegawa, Konosuke Watanabe
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Patent number: 10871901Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.Type: GrantFiled: December 5, 2018Date of Patent: December 22, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
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Patent number: 10853321Abstract: A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. The control device includes a setting unit and a writing/reading unit. The setting unit sets first storage regions obtained by dividing a storage region for each of the storage devices and sets second storage regions obtained by dividing storage regions of all of the storage devices for all of the storage devices. The writing/reading unit manages data stored in the storage devices in units of the second storage regions. The setting unit sets each of the first storage regions so that the first storage region for at least one of the plurality of storage devices includes the entirety of one or more blocks and sets each of the second storage regions to include two or more of the first storage regions.Type: GrantFiled: September 12, 2017Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventors: Yohei Hasegawa, Yoshiki Saito, Shohei Onishi, Hidenori Matsuzaki, Shigehiro Asano
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Patent number: 10644204Abstract: A method of manufacturing a light emitting element includes forming an n-type semiconductor layer that includes an n-type clad layer and AlxGa1-xN (0.1?x?1) as a main component, forming an n-side contact electrode that includes a laminate structure including a Ti layer and a Ru layer, the Ti layer being in contact with the n-type semiconductor layer, and forming an ohmic contact of the n-type semiconductor layer and the Ti layer by a heat treatment.Type: GrantFiled: September 14, 2017Date of Patent: May 5, 2020Assignee: TOYODA GOSEI CO., LTD.Inventors: Yasuhiro Takenaka, Yoshiki Saito, Shinichi Matsui, Daisuke Shinoda, Takashi Hodota, Hironao Shinohara