Patents by Inventor Yoshiki Seo

Yoshiki Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for changing computational tasks on computation nodes to minimize processing time variation
    Patent number: 8214521
    Abstract: Systems and methods are disclosed to process streaming data units (tuples) for an application using a plurality of processing units, the application have a predetermined processing time requirement, by changing an operator-set applied to the tuple by a processing unit, on a tuple-by-tuple basis; estimating code requirement for potential operators based on processing unit capability; and assigning the potential operators to the processing units.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 3, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Masamichi Takagi, Yoshiki Seo, Akio Yamada, Takeo Hosomi
  • SYSTEMS AND METHODS FOR CHANGING COMPUTATIONAL TASKS ON COMPUTATION NODES TO MINIMIZE PROCESSING TIME VARIATION
    Publication number: 20110131578
    Abstract: Systems and methods are disclosed to process streaming data units (tuples) for an application using a plurality of processing units, the application have a predetermined processing time requirement, by changing an operator-set applied to the tuple by a processing unit, on a tuple-by-tuple basis; estimating code requirement for potential operators based on processing unit capability; and assigning the potential operators to the processing units.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Masamichi Takagi, Yoshiki Seo, Akio Yamada, Takeo Hosomi
  • Device for high speed evaluation of logical expressions and high speed vector operations
    Patent number: 5553309
    Abstract: A logical expression operation device is embodied in hardware and is provided with an evaluation value operation means to operate logical expressions in vector data format and an evaluation value holding means to hold the operation result as intermediate evaluation values, and a control means which sequentially reads out the components of the logical expressions, judges the type of read component and controls the applicable means based on the judgment result and the status of the means to execute evaluation of said logical expressions with omitting the operation by the evaluation value operation means for a part in the logical expression corresponding to the secondary operated data of a particular operator.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 3, 1996
    Assignees: Japan Atomic Energy Research Institute, NEC Corporation
    Inventors: Kiyoshi Asai, Takeshi Nishikawa, Yoshiki Seo