Patents by Inventor Yoshiki Sota

Yoshiki Sota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180325427
    Abstract: Provided is an imaging device capable of improving imaging accuracy while suppressing increase in a size of the device and cost thereof. An imaging device includes: a light source which is a semiconductor laser that radiates infrared light to an imaging target; a polarizing filter that blocks light that is reflected by a surface of the imaging target and transmits light that is reflected inside the imaging target; and an image sensor that receives the light that is transmitted through the polarizing filter and captures an image of the imaging target.
    Type: Application
    Filed: September 29, 2016
    Publication date: November 15, 2018
    Inventors: SHIN ITOH, KAZUHIRO TSUCHIDA, TOHRU MURATA, HIROAKI YAMAMOTO, AKIRA ARIYOSHI, KEISUKE MIYAZAKI, YOSHIKI SOTA
  • Patent number: 9537065
    Abstract: Improves light extraction efficiency. A light emitting device 1 using a white resin molding package 5 integrally molded with lead frames 3, 4 constituting an electrode corresponding to one or a plurality of light emitting element 2 and white resin, wherein an area in a plane view of a white resin surface on a reflective surface that is level with amounting surface of the light emitting element 2 is configured to be larger than total area in a plane view occupied by surfaces of the lead frames 3, 4 and the light emitting element. Further, a step section is formed on the surfaces of lead frames 3, 4, white resin is filled in the step section, and the area of white resin surface on a reflective surface where the light emitting element 2 is mounted is increased.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 3, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiki Sota, Masayuki Ohta, Kazuo Tamaki, Shinji Yamaguchi, Shin Itoh, Tomoshi Kimura, Masaki Tatsumi
  • Patent number: 9537072
    Abstract: Pkg resin crack is suppressed after dicing. A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 3, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Sota, Kazuo Tamaki
  • Publication number: 20160353544
    Abstract: Provided is a light-emitting device that is capable of adjusting color temperature through the supply of electric power from a single power supply. The light-emitting device includes an anode electrode land, a cathode electrode land, and first and second wires through which the anode electrode land and the cathode electrode land are connected to each other. The first wire is higher in electric resistance than the second wire. The color temperature of light that is emitted by a whole light-emitting unit including a first light-emitting unit electrically connected to the first wire and a second light-emitting unit electrically connected to the second wire is adjustable.
    Type: Application
    Filed: January 7, 2015
    Publication date: December 1, 2016
    Inventors: Nobumasa KANEKO, Tomokazu NADA, Makoto AGATANI, Toshio HATA, Osamu JINUSHI, Yoshiki SOTA, Naveen Venkata Rama DEVISETTI, Kazuaki KANEKO, Hiroaki ONUMA
  • Publication number: 20160254430
    Abstract: Pkg resin crack is suppressed after dicing. A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7.
    Type: Application
    Filed: March 30, 2016
    Publication date: September 1, 2016
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki SOTA, Kazuo TAMAKI
  • Patent number: 9331254
    Abstract: Pkg resin crack is suppressed after dicing. A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 3, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Sota, Kazuo Tamaki
  • Publication number: 20140175501
    Abstract: Pkg resin crack is suppressed after dicing. A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7.
    Type: Application
    Filed: May 31, 2012
    Publication date: June 26, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Sota, Kazuo Tamaki
  • Publication number: 20140159076
    Abstract: Improves light extraction efficiency. A light emitting device 1 using a white resin molding package 5 integrally molded with lead frames 3, 4 constituting an electrode corresponding to one or a plurality of light emitting element 2 and white resin, wherein an area in a plane view of a white resin surface on a reflective surface that is level with amounting surface of the light emitting element 2 is configured to be larger than total area in a plane view occupied by surfaces of the lead frames 3, 4 and the light emitting element. Further, a step section is formed on the surfaces of lead frames 3, 4, white resin is filled in the step section, and the area of white resin surface on a reflective surface where the light emitting element 2 is mounted is increased.
    Type: Application
    Filed: May 31, 2012
    Publication date: June 12, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Sota, Masayuki Ohta, Kazuo Tamaki, Shinji Yamaguchi, Shin Itoh, Tomoshi Kimura, Masaki Tatsumi
  • Patent number: 8749263
    Abstract: A semiconductor apparatus according to the present invention with a semiconductor element implemented on an insulated substrate comprises: a substrate front surface electrode formed on a front surface side of the insulated substrate and connected with an element electrode of the semiconductor element; a substrate back surface electrode formed on a back surface side of the insulated substrate and electrically connected with the substrate front surface electrode; and a plurality of connection electrodes, extending in a thickness direction of the insulated substrate from one side to the other side of a front surface and a back surface thereof, for electrically connecting the substrate front surface electrode with the substrate back surface electrode, where the substrate front surface electrode or the substrate back surface electrode is formed to have a plane pattern separated for each of the plurality of connection electrodes.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 10, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Ohta, Masaki Tatsumi, Yoshiki Sota, Kazuo Tamaki, Shinji Yamaguchi, Masamichi Harada, Shin Ito, Tomoshi Kimura, Yoshifumi Inada
  • Patent number: 8436456
    Abstract: A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: May 7, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiki Sota, Kazuaki Tatsumi
  • Publication number: 20120049882
    Abstract: A semiconductor apparatus according to the present invention with a semiconductor element implemented on an insulated substrate comprises: a substrate front surface electrode formed on a front surface side of the insulated substrate and connected with an element electrode of the semiconductor element; a substrate back surface electrode formed on a back surface side of the insulated substrate and electrically connected with the substrate front surface electrode; and a plurality of connection electrodes, extending in a thickness direction of the insulated substrate from one side to the other side of a front surface and a back surface thereof, for electrically connecting the substrate front surface electrode with the substrate back surface electrode, where the substrate front surface electrode or the substrate back surface electrode is formed to have a plane pattern separated for each of the plurality of connection electrodes.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masayuki OHTA, Masaki Tatsumi, Yoshiki Sota, Kazuo Tamaki, Shinji Yamaguchi, Masamichi Harada, Shin Ito, Tomoshi Kimura, Yoshifumi Inada
  • Publication number: 20110042828
    Abstract: A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
    Type: Application
    Filed: March 16, 2009
    Publication date: February 24, 2011
    Inventors: Yoshiki Sota, Kazuaki Tatsumi
  • Patent number: 7876572
    Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: January 25, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshiki Sota
  • Publication number: 20090184413
    Abstract: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.
    Type: Application
    Filed: September 17, 2008
    Publication date: July 23, 2009
    Inventors: Kazuaki TATSUMI, Yoshiki SOTA
  • Publication number: 20090102049
    Abstract: A semiconductor device has a plurality of external connection lands arranged on a base substrate for an external connection terminal used for electrical connection with an external member. The external connection lands at different arrangement positions have different heights in accordance with a warp of the base substrate which warp the base substrate would have when mounted. Thus, even when the semiconductor device, which attains a thin thickness and a high density, is warped, it is possible to provide a semiconductor device having a high connection yield and high connection reliability between the semiconductor device and a mounting substrate and between the semiconductor devices, and it is possible to provide a layered type semiconductor device using the same, a base substrate and a semiconductor device manufacturing method.
    Type: Application
    Filed: March 26, 2007
    Publication date: April 23, 2009
    Inventors: Katsumasa Murata, Yuji Yano, Yoshiki Sota
  • Publication number: 20070176300
    Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.
    Type: Application
    Filed: January 23, 2007
    Publication date: August 2, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Yoshiki Sota
  • Publication number: 20070035036
    Abstract: The semiconductor device according to the present invention includes a semiconductor chip and a wiring substrate on which a wiring pattern is formed. The wiring pattern includes wire bond terminals being electrically connected, via wires, with pads provided on the semiconductor chip. The wire bond terminals are disposed in a plurality of columns so as to face the pads. When the columns are regarded as the first column to the third column so that the first column is the closest to the pads, the ratio of a pitch between the wire bond terminals belonging to the first column, a pitch between the wire bond terminals belonging to the second column, and a pitch between the wire bond terminals belonging to the third column is 1:2:2. This allows for efficient wiring between the wire bond terminals in a case where wiring with electrolytic plating is impossible. As a result, it is possible to provide a wiring substrate with stable qualities at lower cost.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 15, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Sota, Kazuo Tamaki
  • Patent number: 6979905
    Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 27, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashige Nishida, Yoshiki Sota, Hiroyuki Juso
  • Patent number: RE38806
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai
  • Patent number: RE41826
    Abstract: In a semiconductor device in which a semiconductor chip is stacked on a substrate, an interposer chip having wirings is provided under the semiconductor chip. A bonding pad of the semiconductor chip is electrically connected to a bonding terminal provided on the substrate via the interposer chip by wire bonding. The interposer chip prevents a semiconductor element formed in the semiconductor chip from deteriorating in terms of an electric property and from being physically damaged. Further, the wire bonding strength does not drop. Moreover, it is possible to form a fine wiring pitch for relaying a wire-bonding wire.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: October 19, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashige Nishida, Yoshiki Sota, Hiroyuki Juso