Patents by Inventor Yoshiki Takeda
Yoshiki Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944999Abstract: A vibration device includes a bimorph type piezoelectric element having a first main surface and a second main surface facing each other and a vibration member bonded to the second main surface of the piezoelectric element. The piezoelectric element has a first active region disposed closer to the first main surface between the first and second main surfaces and a second active region disposed closer to the second main surface than the first active region between the first and second main surfaces. When a force generated in the first active region is F1, a force generated in the second active region is F2, and a force by which the vibration member restrains the second active region is Fr, F2?F1?Fr is satisfied.Type: GrantFiled: February 21, 2019Date of Patent: April 2, 2024Assignee: TDK CORPORATIONInventors: Yoshiki Ohta, Hideya Sakamoto, Kazushi Tachimoto, Yoshikazu Shimura, Tetsuyuki Taniguchi, Akihiro Takeda
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Patent number: 11930713Abstract: A piezoelectric element includes a piezoelectric body, an electrode layer, and a reinforcing layer. The piezoelectric body has a first main surface, a second main surface, and a side surface. The first main surface and the second main surface oppose each other. The side surface extends in an opposing direction in which the first main surface and the second main surface oppose each other in such a way as to connect the first main surface and the second main surface. The electrode layer is provided in the piezoelectric body. The reinforcing layer is provided on the first main surface. The electrode layer is provided opposing the first main surface and apart from the side surface. When viewed from the opposing direction, the electrode layer has a corner. When viewed from the opposing direction, the reinforcing layer overlaps the corner.Type: GrantFiled: April 3, 2019Date of Patent: March 12, 2024Assignee: TDK CORPORATIONInventors: Yoshiki Ohta, Hideya Sakamoto, Kazushi Tachimoto, Yoshikazu Shimura, Tetsuyuki Taniguchi, Akihiro Takeda
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Patent number: 7759270Abstract: An environmentally friendly polymerization catalyst for polyalkylene terephthalate which does not use a heavy metal such as antimony, and a method for producing polyalkylene terephthalate using the catalyst. The catalyst for polymerizing a polyalkylene terephthalate is a titanium oxide sol containing an organic solvent as a dispersion medium, the sol has a light transmittance of not less than 50%, the light transmittance being measured by adjusting a concentration of the titanium oxide in the sol to 0.7 g/L and setting an optical path length to 1 cm in a wavelength range of 400 to 800 nm, and the amount of hydroxyl groups per 1 g of titanium oxide is not less than 1.8 mmol.Type: GrantFiled: May 11, 2006Date of Patent: July 20, 2010Assignee: Fuji Titanium Industry Co., Ltd.Inventors: Jinichiro Kato, Yoshiki Takeda, Takafumi Konishi
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Publication number: 20090069529Abstract: An object of the present invention is to provide an environmentally friendly polymerization catalyst of polyalkylene terephthalate which does not use a heavy metal such as antimony. Another object of the present invention is to provide the method of producing polyalkylene terephthalate using the catalyst. The inventive titanium oxide sol for a catalyst for polymerizing a polyalkylene terephthalate is a titanium oxide sol containing an organic solvent as a dispersion medium, wherein the titanium oxide in the sol has a concentration of 0.7 g/L, the sol has a light transmittance of not less than 50%, the light transmittance being measured by setting an optical path length to 1 cm in a wavelength range of 400 to 800 nm, and the amount of hydroxyl groups per 1 g of titanium oxide is not less than 1.8 mmol.Type: ApplicationFiled: May 11, 2006Publication date: March 12, 2009Inventors: Jinichiro Kato, Yoshiki Takeda, Takafumi Konishi
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Patent number: 7226807Abstract: A method of production of a circuit board utilizing electroplating which prevents signal reflection and noise due to unnecessary parts in the circuit patterns when electroplating to form circuit patterns on the board to thereby improve the electrical properties and realize higher density layout of the circuit patterns, including the steps of forming a first electroless plating layer and an overlying first plating resist on a metal foil-clad insulating board, feeding power to the first electroless plating layer to form a first electroplating layer over the first electroless plating layer in resist openings; removing the first plating resist; removing the exposed first electroless plating layer and metal foil to expose the insulating board; forming a second electroless plating layer over the exposed parts of the board and the circuit patterns; forming a second plating resist over that; removing the second electroless plating layer at the resist openings; feeding power to the second electroless plating layer undType: GrantFiled: March 30, 2006Date of Patent: June 5, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideyasu Okazawa, Yoshiki Takeda
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Publication number: 20060223223Abstract: A method of production of a circuit board utilizing electroplating which prevents signal reflection and noise due to unnecessary parts in the circuit patterns when electroplating to form circuit patterns on the board to thereby improve the electrical properties and realize higher density layout of the circuit patterns, including the steps of forming a first electroless plating layer and an overlying first plating resist on a metal foil-clad insulating board, feeding power to the first electroless plating layer to form a first electroplating layer over the first electroless plating layer in resist openings; removing the first plating resist; removing the exposed first electroless plating layer and metal foil to expose the insulating board; forming a second electroless plating layer over the exposed parts of the board and the circuit patterns; forming a second plating resist over that; removing the second electroless plating layer at the resist openings; feeding power to the second electroless plating layer undType: ApplicationFiled: March 30, 2006Publication date: October 5, 2006Inventors: Hideyasu Okazawa, Yoshiki Takeda
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Patent number: 6596807Abstract: A vinyl alcohol polymer composition (II) is produced by a process of providing a reaction liquid comprising a solution containing a vinyl carboxylate polymer and, a first metal alkoxide (I) having at least one functional group and/or an oligomer (I) having at least one functional group obtained from said metal alkoxide (I); a step of simultaneously effecting (a) saponification of said vinyl carboxylate polymer and (b) reaction in which at least part of the functional groups of said metal alkoxide (I) and/or said oligomer (I) participates, thereby obtaining a vinyl alcohol polymer composition (I); and a step of preparing a solution (A) containing said vinyl alcohol polymer composition (I), followed by adding to the solution (A) a second metal alkoxide (II) and/or an oligomer (II) obtained from the metal alkoxide (II) or another solution (B) containing the metal alkoxide (II) and/or the oligomer (II) derived from the metal alkoxide (II), to prepare an intermediate product solution (C), and then removing the solType: GrantFiled: July 30, 2001Date of Patent: July 22, 2003Assignee: Kuraray Co., Ltd.Inventors: Tatsuya Oshita, Goki Uehara, Nobuhisa Senda, Yoshiki Takeda, Yukiatsu Komiya, Syuichi Kanao, Shigeki Takada, Naoki Kawakami, Kanenori Ito
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Publication number: 20020055579Abstract: A vinyl alcohol polymer composition (II) is produced by a process of providing a reaction liquid comprising a solution containing a vinyl carboxylate polymer and, a first metal alkoxide (I) having at least one functional group and/or an oligomer (I) having at least one functional group obtained from said metal alkoxide (I); a step of simultaneously effecting (a) saponification of said vinyl carboxylate polymer and (b) reaction in which at least part of the functional groups of said metal alkoxide (I) and/or said oligomer (I) participates, thereby obtaining a vinyl alcohol polymer composition (I); and a step of preparing a solution (A) containing said vinyl alcohol polymer composition (I), followed by adding to the solution (A) a second metal alkoxide (II) and/or an oligomer (II) obtained from the metal alkoxide (II) or another solution (B) containing the metal alkoxide (II) and/or the oligomer (II) derived from the metal alkoxide (II), to prepare an intermediate product solution (C), and then removing the solType: ApplicationFiled: July 30, 2001Publication date: May 9, 2002Applicant: Kuraray Co., Ltd.Inventors: Tatsuya Oshita, Goki Uehara, Nobuhisa Senda, Yoshiki Takeda, Yukiatsu Komiya, Syuichi Kanao, Shigeki Takada, Naoki Kawakami, Kanenori Ito
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Patent number: 6081426Abstract: A semiconductor package uses no thermosetting adhesive for mounting a heat slug thereon, which adhesive requires a strict control during the storage and the production thereof. A semiconductor package comprises a circuit board having respective surfaces and an opening; a conductive layer formed on one of the surfaces of the circuit board so that the conductive layers are retracted from a peripheral edge of the opening by a certain distance; a heat slug attached to the one surface of the circuit board by means of solder so that the opening is closed at the one surface and opened at the other surface to form a cavity within which a semiconductor element mounting area is defined.Type: GrantFiled: March 17, 1999Date of Patent: June 27, 2000Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yoshiki Takeda, Takemi Machida, Fumio Kuraishi
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Patent number: 5905634Abstract: A semiconductor package uses no thermosetting adhesive for mounting a heat slug thereon, which adhesive requires a strict control during the storage and the production thereof. A semiconductor package comprises a circuit board having respective surfaces and an opening; a conductive layer formed on one of the surfaces of the circuit board so that the conductive layers are retracted from a peripheral edge of the opening by a certain distance; a heat slug attached to the one surface of the circuit board by means of solder so that the opening is closed at the one surface and opened at the other surface to form a cavity within which a semiconductor element mounting area is defined; and the heat slug is provided with a groove along a periphery of the semiconductor element mounting area and adjacent the peripheral edge of the opening.Type: GrantFiled: September 15, 1997Date of Patent: May 18, 1999Assignee: Shinko Electric Industries, Co., Ltd.Inventors: Yoshiki Takeda, Takemi Machida, Fumio Kuraishi
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Patent number: 5854094Abstract: A process for manufacturing a metal plane support for making multi-layer lead frames adapted to be used for semiconductor devices. The lead frame support is made of a single thin metal strip having a plurality of lead frames continuously arranged in the longitudinal direction, the metal plane support is also made of a single thin metal strip and includes a plurality of metal planes, such as power supply planes, ground planes of the like, continuously arranged in the longitudinal direction corresponding to said plurality of lead frames. A pair of side rails are extending in the longitudinal direction for supporting the metal planes therebetween. The metal planes are connected to the rails via separating portions for removing the rails from the metal planes, after the metal planes are adhered to the corresponding lead frames.Type: GrantFiled: October 1, 1996Date of Patent: December 29, 1998Assignees: Shinko Electric Industries Co., Ltd., Intel CorporationInventors: Hirofumi Fujii, Yoshiki Takeda, Mitsuharu Shimizu
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Patent number: 5410180Abstract: A metal plane support structure of a semiconductor device multi-layer lead frame having one or more metal planes, of different types, arranged in stacked and aligned relationship with and adhered to a corresponding lead frame. Metal planes of a common type are defined in a corresponding metal strip, at longitudinally spaced positions, the metal strip having a pair of side rails along the longitudinal edges thereof, integral support bars extending transversely of the side rails and interconnecting the metal planes to the side rails and section bars extending between and integrally interconnecting the side rails, each section bar disposed between two adjacent metal planes. Separating portions are formed in aligned relationship in the support bars and section bars. The lead frames are defined, further, at longitudinally spaced positions corresponding to the spacing of the metal planes, in a further metal strip having a smaller transverse dimension than that of each metal plane strip.Type: GrantFiled: July 26, 1993Date of Patent: April 25, 1995Assignees: Shinko Electric Industries Co., Ltd., Intel CorporationInventors: Hirofumi Fujii, Yoshiki Takeda, Mitsuharu Shimizu
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Patent number: 5291060Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.Type: GrantFiled: December 3, 1992Date of Patent: March 1, 1994Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.Inventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 5281556Abstract: A process for manufacturing a multi-layer semiconductor lead frame comprising the step of adhering a lead frame strip to a metal power supply plane strip and a metal ground plane strip.Type: GrantFiled: May 16, 1991Date of Patent: January 25, 1994Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsuharu Shimizu, Yoshiki Takeda
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Patent number: 5237202Abstract: A multi-layer lead frame is provided with a lead frame body made of a metal strip and having a plurality of inner leads including respective tips which define an opening. A power supply metal plane is adhered to the inner leads and a ground metal plane is adhered to the power supply metal plane by insulative adhesive layers. These metal planes are provided with first wire bonding areas and through holes in the vicinity thereof. A semiconductor device comprises such a multi-layer lead frame, a semiconductor chip mounted on a stage thereof, bonding-wires electrically connecting the chip to the areas, and a resin integrally molding the multi-layer lead frame, the chip, and the bonding-wires in such a manner that the through holes are filled with the resin.Type: GrantFiled: December 9, 1991Date of Patent: August 17, 1993Assignees: Shinko Electric Industries Co., Ltd, Intel CorporationInventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 5235209Abstract: A multi-layer lead frame for a semiconductor device comprises a lead frame body made of a metal strip having a first opening and a plurality of inner leads having respective innertips which define the opening. A metal plane independent from the lead frame body and adhered to the inner leads by an insulation adhesive film, has an inner periphery defining a second opening corresponding to the first opening. The inner periphery of the insulation film protrudes slightly from the inner tips of the inner leads.Type: GrantFiled: September 3, 1991Date of Patent: August 10, 1993Assignees: Shinko Electric Industries Co., Ltd., Intel Corp.Inventors: Mitsuharu Shimizu, Yoshiki Takeda, Hirofumi Fujii
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Patent number: 4597311Abstract: A final speed-reduction gearing assembly is mounted within a trans-axle casing which carries an output drive pinion shaft thereon, the gearing assembly comprising a ring gear in mesh with a drive pinion integral with the drive pinion shaft, and a differential gear unit integrally connected at the outer case thereof with the ring gear, the outer case of the unit being rotatably supported at the opposite ends thereof by first and second axially spaced bearings which are respectively mounted on first and second carrier portions of the trans-axle casing. A retainer member is arranged to fasten the first bearing to the first carrier portion of the casing and to be radially detachable for adjustment of a preload axially acting on the bearings, and an annular shim plate is disposed between the first bearing and the first carrier portion in such a way as to be removable radially for adjustment of the preload.Type: GrantFiled: March 21, 1983Date of Patent: July 1, 1986Assignee: Toyota Jidosha Kabushiki KaishaInventor: Yoshiki Takeda
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Patent number: D1016002Type: GrantFiled: August 23, 2022Date of Patent: February 27, 2024Assignee: Koki Holdings Co., Ltd.Inventors: Yoshiki Aoki, Shuji Takeda, Shota Kanno
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Patent number: D1016003Type: GrantFiled: February 8, 2023Date of Patent: February 27, 2024Assignee: Koki Holdings Co., Ltd.Inventors: Yoshiki Aoki, Ibuki Kanda, Shuji Takeda, Shota Kanno