Patents by Inventor Yoshiko Araki

Yoshiko Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6303440
    Abstract: A method of manufacturing the semiconductor memory comprises element described below; (a) forming a first oxide film on a semiconductor substrate; (b) forming a polysilicon electrode on the first oxide film by sub-steps of forming a low impurity density polysilicon layer, forming a high impurity density polysilicon layer, and forming a low impurity density polysilicon layer in this order; (c) forming a second oxide film on the polysilicon electrode.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: October 16, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiko Araki, Seiichi Mori
  • Patent number: 6166419
    Abstract: The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiko Araki
  • Patent number: 5989959
    Abstract: A silicon nitride film and a silicon oxide film are deposited in that order on a WSi film. In a single session of lithography, the gate electrode of a memory cell and the gate electrode of a transistor constituting a peripheral circuit are formed. The silicon oxide film makes a mask used to form a floating gate of the memory cell. The silicon nitride film makes a mask used to form a common source region by etching a gate oxide film and a field oxide film. The silicon nitride film covers the WSi film to prevent impurities from entering the WSi film when impurities are introduced into the common source region. This prevents abnormal oxidation in a subsequent process.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: November 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiko Araki
  • Patent number: 5882994
    Abstract: A method of manufacturing the semiconductor memory comprises a plurality of steps. The steps include forming a first oxide film on a semiconductor substrate, forming a polysilicon electrode on the first oxide film by the sub-steps of forming a low impurity density polysilicon layer, forming a high impurity density polysilicon layer, and forming a low impurity density polysilicon layer in this order, and forming a second oxide film on the polysilicon electrode.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: March 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiko Araki, Seiichi Mori
  • Patent number: 5658812
    Abstract: The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: August 19, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiko Araki