Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 ?m or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.

Abstract: In the semiconductor memory device, the size in the row direction of the memory cell region having no through-hole therein is made smaller than that of the memory cell region having a through-hole therein. Thus, even if the semiconductor memory device has a double-layered bit line configuration and the size in the row direction of the memory cell region increases due to the through-hole connecting the bit lines in the first and second layers or the like, it is possible to prevent the increase in size of the memory cell region, and hence, the increase in area of the memory cell array.

Abstract: An output buffer is connected to a first power supply line and a first ground line, and a strobe buffer is connected to a second power supply line and a second ground line. The first power supply line is connected to a first pad, the first ground line is connected to a second pad, the second power supply line is connected to a third pad, and the second ground line is connected to a fourth pad, respectively. The first and second power supply lines are not connected inside the chip, and the first and second ground lines are not connected inside the chip. The first and third pads are separately connected to the respective lead terminals, and the second and fourth pads are separately connected to the respective lead terminals.

Abstract: An input protection circuit device for protecting a device in a semiconductor circuit device when a surge current is applied to a signal input terminal of the semiconductor circuit device is provided. The input circuit device includes an nMOS transistor between an input signal line connecting an input pad and an internal circuit and a first power supply (Vcc), and having a gate electrode connected to GND via a resistor-C, and a diode between the input signal line and GND. When a positive surge current higher than the potential of the first power supply (Vcc) is applied to the input pad, and when a negative surge current lower than the potential of GND is applied, the surge current is moderated by the nMOS transistor and by the diode, respectively, to prevent the flow of the surge current to the internal circuit.