Patents by Inventor Yoshiko Kokawa

Yoshiko Kokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5721145
    Abstract: The present invention is mainly characterized in that a semiconductor substrate improved so as to maintain a gettering effect for a long time can be obtained. A polycrystalline silicon film is formed on the rear surface of a semiconductor substrate. A silicon oxide film and silicon nitride film are formed over the rear surface of semiconductor substrate so as to cover polycrystalline silicon film.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: February 24, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Kusakabe, Yoshiko Kokawa, Masahiro Sekine
  • Patent number: 5419786
    Abstract: A semiconductor substrate allowing reduction of crystal defects in a device formation region of an epitaxial silicon layer and allowing control of the amount of internal precipitation defects of the single crystal silicon substrate, a method of manufacturing such semiconductor substrate, and a semiconductor device utilizing such semiconductor substrate are disclosed. The semiconductor substrate includes a single crystal silicon substrate, an epitaxial silicon layer, and a polycrystalline silicon layer. The interstitial oxygen concentration of the single crystal silicon substrate is set within the range of 12.5-14.0.times.10.sup.17 (atoms/cm3) according to the old ASTM specification. The epitaxial silicon layer is formed on the top surface of the single crystal silicon substrate. The polycrystalline silicon layer is formed at least on the rear surface of the single crystal silicon substrate to a thickness of at least 1 .mu.m.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: May 30, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiko Kokawa, Kenji Kusakabe
  • Patent number: 5381032
    Abstract: A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: January 10, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiko Kokawa, Tohru Koyama, Kenji Kusakabe, Katsuhiko Tamura, Yasuna Nakamura
  • Patent number: 5221630
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: June 22, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe
  • Patent number: 5177569
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: January 5, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe