Abstract: A classification circuit generates first information for classifying an operating state of a power semiconductor element into one of a plurality of predetermined operating regions. A selector circuit generates second information for selecting a plurality of modes with different switching speeds, based on a user input. A characteristic control circuit stores a drive adjustment signal in advance for each of combinations of the operating regions and the modes and outputs the drive adjustment signal in a combination of one operating region and one mode that is selected in accordance with the first information and the second information. A gate drive circuit charges/discharges a gate at a charge rate and a discharge rate variably set in accordance with the drive adjustment signal from the characteristic control circuit, at the time of on/off of the power semiconductor element.

Abstract: A power semiconductor element drive adjustment circuit is provided with a difference unit to calculate a difference value between a normalized value of the differential value of the collector-emitter voltage and a normalized value of the differential value of the collector current, a comparison unit to compare the difference value with a comparison reference value, a drive control unit to generate, on the basis of a comparison result of the comparison unit, a drive adjustment signal that adjusts a drive signal for the power semiconductor element, and a drive variable circuit to output, on the basis of the drive adjustment signal, the drive signal for the power semiconductor element.

Abstract: A semiconductor module includes a semiconductor chip, an insulating substrate, a relay board, and a heat-dissipating component. The insulating substrate includes a main circuit pattern and an insulating layer. The main circuit pattern is electrically connected to the semiconductor chip. The relay board sandwiches the semiconductor chip together with the main circuit pattern in a direction in which the insulating layer and the semiconductor chip sandwich the main circuit pattern. The relay board is electrically connected to the main circuit pattern through the semiconductor chip. The heat-dissipating component is sandwiched between the insulating substrate and the relay board in the sandwiching direction. The main circuit pattern at least partially surrounds the heat-dissipating component on the insulating layer.

Abstract: A parallel driving device that drives parallel-connected semiconductor elements includes a control unit and a gate driving circuit. The control unit detects a temperature difference between the semiconductor elements on the basis of detected values by temperature sensors that detect temperatures of the individual semiconductor elements. The control unit generates a control signal for changing the timing at which to turn on a first semiconductor element specified from the semiconductor elements on the basis of the temperature difference. The gate driving circuit generates a first driving signal for driving the semiconductor elements, and generates a second driving signal that is the first driving signal delayed on the basis of the control signal, and applies the second driving signal to the first semiconductor element.

Abstract: A power semiconductor module includes a plurality of self-arc-extinguishing semiconductor elements, a printed wiring board, a plurality of conductive joining members, and a plurality of conductive gate wires. The printed wiring board includes an insulating substrate, a source conductive pattern, and a gate conductive pattern. The plurality of self-arc-extinguishing semiconductor elements each include a source electrode and a gate electrode. The source electrodes are joined to the source conductive pattern by means of the plurality of conductive joining members. The plurality of conductive gate wires connect the gate electrodes and the gate conductive pattern.

Abstract: A classification circuit generates first information for classifying an operating state of a power semiconductor element into one of a plurality of predetermined operating regions. A selector circuit generates second information for selecting a plurality of modes with different switching speeds, based on a user input. A characteristic control circuit stores a drive adjustment signal in advance for each of combinations of the operating regions and the modes and outputs the drive adjustment signal in a combination of one operating region and one mode that is selected in accordance with the first information and the second information. A gate drive circuit charges/discharges a gate at a charge rate and a discharge rate variably set in accordance with the drive adjustment signal from the characteristic control circuit, at the time of on/off of the power semiconductor element.

Abstract: A parallel driving device that drives parallel-connected semiconductor elements includes a control unit and a gate driving circuit. The control unit detects a temperature difference between the semiconductor elements on the basis of detected values by temperature sensors that detect temperatures of the individual semiconductor elements. The control unit generates a control signal for changing the timing at which to turn on a first semiconductor element specified from the semiconductor elements on the basis of the temperature difference. The gate driving circuit generates a first driving signal for driving the semiconductor elements, and generates a second driving signal that is the first driving signal delayed on the basis of the control signal, and applies the second driving signal to the first semiconductor element.

Abstract: An increased accuracy in detecting deterioration of a semiconductor device can be achieved. A first metal pattern and a second metal pattern are connected to a controller. A bonding wire connects the first metal pattern and an emitter electrode. A linear conductor is connected between a first electrode pad and a second electrode pad. First bonding wires connect the first electrode pad and the second metal pattern. Second bonding wires connect the second electrode pad and the second metal pattern. The controller detects the deterioration of the semiconductor device when a potential difference between the first metal pattern and the second metal pattern is above a threshold.

Abstract: An emitter interconnection connecting the emitter of a semiconductor switching element to a negative electrode is different in one or both of length and width from an emitter interconnection connecting the emitter of a semiconductor switching element to the negative electrode. At the time of switching, an induced electromotive force is generated at a gate control wire, or at a gate pattern, or at an emitter wire, by at least one of a current flowing through a positive electrode and a current flowing through the negative electrode, so as to reduce the difference between the emitter potential of the semiconductor switching element and the emitter potential of the semiconductor switching element caused by the difference.

Abstract: A short-circuit protection circuit for a self-arc-extinguishing type semiconductor element includes a first protection circuit and a second protection circuit. The first protection circuit is configured to reduce a voltage between a control electrode and a first main electrode of the self-arc-extinguishing type semiconductor element when detecting overcurrent flowing between the first main electrode and a second main electrode. The second protection circuit is configured to: detect current flowing in an interconnection adapted to supply the drive voltage; determine, based on the detected current, whether the first protection circuit is in an operating state; and change the drive voltage to turn off the self-arc-extinguishing type semiconductor element when the first protection circuit is in the operating state.

Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Abstract: An emitter interconnection connecting the emitter of a semiconductor switching element to a negative electrode is different in one or both of length and width from an emitter interconnection connecting the emitter of a semiconductor switching element to the negative electrode. At the time of switching, an induced electromotive force is generated at a gate control wire, or at a gate pattern, or at an emitter wire, by at least one of a current flowing through a positive electrode and a current flowing through the negative electrode, so as to reduce the difference between the emitter potential of the semiconductor switching element and the emitter potential of the semiconductor switching element caused by the difference.

Abstract: Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern.

Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Abstract: A power switching apparatus includes a plurality of semiconductor switching devices connected in parallel with each other and a plurality of balance resistor units. The plurality of balance resistor units each have one end connected to a control electrode of an associated semiconductor switching device and the other end to which a common control signal is input. Each balance resistor unit is configured to have a resistance value switched between different values depending on whether the plurality of semiconductor switching devices are turned on or turned off in accordance with the control signal.

Abstract: An increased accuracy in detecting deterioration of a semiconductor device can be achieved. A first metal pattern and a second metal pattern are connected to a controller. A bonding wire connects the first metal pattern and an emitter electrode. A linear conductor is connected between a first electrode pad and a second electrode pad. First bonding wires connect the first electrode pad and the second metal pattern. Second bonding wires connect the second electrode pad and the second metal pattern. The controller detects the deterioration of the semiconductor device when a potential difference between the first metal pattern and the second metal pattern is above a threshold.

Abstract: It is an object to provide a pressure-contact power semiconductor device and a power semiconductor core module which are capable of properly reducing their sizes. Each power semiconductor core module includes the following: a plurality of power semiconductor chips including a plurality of self-turn-off semiconductor elements and a plurality of diodes adjacent to each other in plan view; and a plurality of first springs disposed between an upper metal plate and a conductive cover plate. The plurality of self-turn-off semiconductor elements of each power semiconductor core module are arranged along any one of an L-shaped line, a cross-shaped line, and a T-shaped line in plan view.

Abstract: Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern.

Abstract: A power switching apparatus includes a plurality of semiconductor switching devices connected in parallel with each other and a plurality of balance resistor units. The plurality of balance resistor units each have one end connected to a control electrode of an associated semiconductor switching device and the other end to which a common control signal is input. Each balance resistor unit is configured to have a resistance value switched between different values depending on whether the plurality of semiconductor switching devices are turned on or turned off in accordance with the control signal.

Abstract: A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is.