Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

Abstract: A computer system including a plurality of element processors, and an interconnecting network for connecting the element processors. Each element processor includes a processor, a memory, and a network interface circuit for exchanging messages with the interconnecting network. Each element processor is provided with a message passing library for communicating with user processes running therein and a direct inter-memory data transfer library for communicating with the message passing library and controlling the network interface circuit. The network interface circuit includes a memory read circuit connected to the memory, and a message assembly circuit connected to to memory read circuit for generating a message to be transferred to a destination element processor through said interconnecting network.

Abstract: Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

Abstract: A parallel computer using a simply structured network which allows loads on message-transferring routes to be as equally distributed as possible and which eases possible conflict between different types of messages being transferred. Given a message to be transmitted, each processor (PE) on the network references a property setup table to determine property information depending on the message type and places the information into the message. For example, a route bit RB as the property information is set to "0" or "1" depending on whether the message is originated by the sending PE or is a message acknowledging the receipt of another message. According to the RB bit in the received message, a route instruction circuit in each exchange switch (EX) references a route instruction table to determine the message destination that depends on the receiving PE number designated by the message. Each EX has a plurality of virtual channel circuits.

Abstract: In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks.

Abstract: Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor.

Abstract: In a step for bonding a color filter to a solid-state color-image sensor chip with an adhesive which is curable not only by light or more particularly ultraviolet-ray irradiation but also by heating, pre-curing or partial curing is effected by irradiating light rays after the color filter and the chip has been pressed against each other and correctly aligned with each other in a bonding device and then the chip with the partially-bonded color filter is removed from the bonding device and complete curing of the adhesive is accomplished by heating. According to one embodiment of the present invention the bonding step is carried out in an atmosphere containing the oxygen so that the adhesive which has been squeezed out from the space between the color filter and the chip may be prevented from being cured and subsequently removed in a simple manner.

Abstract: In a step for bonding a color filter to a solid-state image sensor so as to provide a color-sensitive image sensor (to be referred to as "a color-image sensor" in this specification), a method for bonding the color filter to the image sensor with an adhesive which is curable by ultraviolet radiation and also the constructions of color filters and image sensors which can facilitate the bonding step.

Abstract: In a step for bonding a color filter to a solid-state color-image sensor chip with an adhesive which is curable not only by light or more particularly ultraviolet-ray irradiation but also by heating, pre-curing or partial curing is effected by irradiating light rays after the color filter and the chip has been pressed against each other and correctly aligned with each other in a bonding device and then the chip with the partially-bonded color filter is removed from the bonding device and complete curing of the adhesive is accomplished by heating. According to one embodiment of the present invention the bonding step is carried out in an atmosphere containing the oxygen so that the adhesive which has been squeezed out from the space between the color filter and the clip may be prevented from being cured and subsequently removed in a simple manner.