Patents by Inventor Yoshimasa Inamoto

Yoshimasa Inamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220068652
    Abstract: Disclosed is a plasma etching method for a substrate that enables formation of various forward-tapered shapes. The plasma etching method disclosed includes the steps of: (i) placing, in a chamber, a substrate 10 including a compound semiconductor layer 11 formed of a Group III-V compound semiconductor, and a resist mask 12 disposed on one principal surface 11a of the compound semiconductor layer 11; and (ii) plasma etching the compound semiconductor layer 11 and the resist mask 12 by exposing the compound semiconductor layer 11 and the resist mask 12 to a plasma, thereby forming a slope 11s that forms a forward-tapered shape on the compound semiconductor layer 11. The Group III-V compound semiconductor includes Ga and As. The plasma etching in the step (ii) is performed using, as an etching gas, a gas mixture including nitrogen gas and a gas containing chlorine.
    Type: Application
    Filed: August 19, 2021
    Publication date: March 3, 2022
    Inventor: Yoshimasa INAMOTO
  • Patent number: 9073385
    Abstract: A substrate placement process uses a tray in which a plurality of substrate receiving holes are provided to receive substrates and which has substrate support portions protruding from inner walls of the substrate receiving holes. The tray is placed onto a tray support portion of a substrate stage and places substrates onto substrate holding portions, respectively, so that edge portions of the substrates projected beyond end edges of the substrate holding portions and are apart from the substrate support portions. The first plasma processing process reduces internal pressure of a chamber and supplies a process gas thereto to fulfill plasma processing for the individual substrates.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: July 7, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Ryota Furukawa, Yoshimasa Inamoto, Tatsuhiro Mizukami
  • Publication number: 20130168353
    Abstract: A process for, with use of a tray in which substrate receiving holes are provided and which has substrate support portions protruding from inner walls of the substrate receiving holes, placing the tray onto a tray support portion of a substrate stage and placing substrates onto the substrate holding portions, so that edge portions of the substrates projected out of end edges of the substrate holding portions and the substrate support portions are separated; a process for reducing pressure in a chamber and supplying a process gas thereto to fulfill plasma processing for the substrates; and a process for, with the tray and the substrates placed on the substrate stage, reducing the pressure in the chamber and supplying a process gas to fulfill plasma processing so that by-products stuck to edge portions of the substrates and the substrate support portions are removed.
    Type: Application
    Filed: September 29, 2011
    Publication date: July 4, 2013
    Inventors: Shogo Okita, Ryota Furukawa, Yoshimasa Inamoto, Tatsuhiro Mizukami
  • Patent number: 8449712
    Abstract: An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface to be cleaned of at least either one of a part, such as a semiconductor device, and a substrate with atmospheric pressure plasma for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface to be cleaned and its vicinity with a first inert gas before the irradiation of the atmospheric pressure plasma is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part and an electrode on the substrate before the inert gas atmosphere maintaining step is ended. The electrode surface is thereby plasma-cleaned without the possibility of damaging the part to be bonded to the substrate, and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: May 28, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshimasa Inamoto, Hachiro Nakatsuji, Kazuhiro Inoue, Hiroyuki Tsuji
  • Publication number: 20090145546
    Abstract: An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface to be cleaned of at least either one of a part, such as a semiconductor device, and a substrate with atmospheric pressure plasma for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface to be cleaned and its vicinity with a first inert gas before the irradiation of the atmospheric pressure plasma is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part and an electrode on the substrate before the inert gas atmosphere maintaining step is ended. The electrode surface is thereby plasma-cleaned without the possibility of damaging the part to be bonded to the substrate, and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.
    Type: Application
    Filed: June 22, 2007
    Publication date: June 11, 2009
    Applicant: Panasonic Corporation
    Inventors: Yoshimasa Inamoto, Hachiro Nakatsuji, Kazuhiro Inoue, Hiroyuki Tsuji
  • Patent number: 5318668
    Abstract: The invention provides an improved dry etching method for selectively etching a silicon nitride layer 3 formed on the surface of a SiO.sub.2 layer 2 formed on a p-type semiconductor substrate, the method comprising the steps of supplying a mixed gas of HBr and ClF.sub.3 to a reaction chamber wherein SiBr.sub.4, caused, during the dry etching, by a reaction of the silicon nitride layer 3 and the HBr contained in the mixed gas, partly deposits on an etching wall of the p-type semiconductor substrate 1 while at the same time an excess of the SiBr.sub.4 reacts, between the p-type semiconductor substrate 1 and a wall of the reaction chamber, with the ClF.sub.3 contained in the mixed gas to produce a fluoride. The fluoride thus produced can be easily discharged to the outside, since it is more volatile.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: June 7, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tokuhiko Tamaki, Shinichi Imai, Tadashi Kimura, Yoshimasa Inamoto