Patents by Inventor Yoshimasa Kawase

Yoshimasa Kawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8735181
    Abstract: A measuring device measures a gate length of a plurality of gate electrodes formed on a wafer. A calculation device calculates data of an ion implantation dosage for making uniform a threshold voltage in a wafer surface on the basis of distribution of the gate length in a wafer surface measured by the measuring device. The ion implantation device implants ions into the wafer on the basis of the data of the ion implantation dosage calculated by the calculation device.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Fujii, Yoshimasa Kawase, Hisato Oyamatsu, Takeshi Shibata
  • Patent number: 7557040
    Abstract: A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Yoshimasa Kawase, Toshihiko Iinuma, Haruko Akutsu, Kyoichi Suguro
  • Publication number: 20090114853
    Abstract: A measuring device measures a gate length of a plurality of gate electrodes formed on a wafer. A calculation device calculates data of an ion implantation dosage for making uniform a threshold voltage in a wafer surface on the basis of distribution of the gate length in a wafer surface measured by the measuring device. The ion implantation device implants ions into the wafer on the basis of the data of the ion implantation dosage calculated by the calculation device.
    Type: Application
    Filed: October 15, 2008
    Publication date: May 7, 2009
    Inventors: Osamu FUJII, Yoshimasa KAWASE, Hisato OYAMATSU, Takeshi SHIBATA
  • Patent number: 7402444
    Abstract: A method of manufacturing a semiconductor device using a wafer emissivity calculated from a wafer reflectivity to calculate a wafer temperature and to calculate target values for heat source optical intensities provided to a plurality of heat sources which heat the wafer and a substrate peripheral structure.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimasa Kawase, Hiroshi Itokawa
  • Patent number: 7247867
    Abstract: An ion implanter includes a sample stage for setting a sample having a main surface, an ion generating section configured to generate a plurality of ions, the ion generating section including a container into which an ion source gas is introduced and a filament for emitting thermal electrons provided in the container, an implanting section configured to implants an ion beam containing the plurality of ions in the main surface of the sample, and a control section configured to control a position of the sample or a spatial distribution of electrons emitted from the filament so that a direction of eccentricity of a center of gravity of the ion beam coincides with a direction of a normal line of the main surface.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Yoshimasa Kawase, Kyoichi Suguro
  • Publication number: 20070166977
    Abstract: A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 19, 2007
    Inventors: Hiroshi Itokawa, Yoshimasa Kawase, Toshihiko Iinuma, Haruko Akutsu, Kyoichi Suguro
  • Publication number: 20070075272
    Abstract: A method of manufacturing a semiconductor device by processing a wafer, comprises: measuring a reflectivity of a substrate peripheral structure before heating, the substrate peripheral structure being placed close to the wafer and being heated simultaneously with the wafer by a plurality of heat sources; measuring a wafer reflectivity of the wafer before the heating; calculating a wafer emissivity of the wafer from the wafer reflectivity; measuring a wafer radiation intensity of radiation emitted from the wafer during the heating; calculating a wafer temperature of the wafer from the wafer emissivity and the wafer radiation intensity; calculating a target value of on-wafer optical intensity on the wafer so that the wafer temperature becomes a preset temperature; calculating a target value of optical intensity on the substrate peripheral structure from a difference between the reflectivity of the substrate peripheral structure and the wafer reflectivity so that incident light being incident on the substrate pe
    Type: Application
    Filed: September 13, 2006
    Publication date: April 5, 2007
    Inventors: Yoshimasa Kawase, Hiroshi Itokawa
  • Patent number: 7145658
    Abstract: An apparatus for evaluating semiconductor material having a pump laser configured to irradiate a pump beam modulated at a modulation frequency on a semiconductor wafer, a probe laser configured to irradiate a probe beam on the semiconductor wafer, and a detector configured to detect a reflection of the probe beam from the semiconductor wafer.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: December 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruko Akutsu, Katsumi Rikimaru, Kyoichi Suguro, Tatsuya Shima, Yoshimasa Kawase, Atsushi Murakoshi
  • Publication number: 20060017017
    Abstract: An ion implanter includes a sample stage for setting a sample having a main surface, an ion generating section configured to generate a plurality of ions, the ion generating section including a container into which an ion source gas is introduced and a filament for emitting thermal electrons provided in the container, an implanting section configured to implants an ion beam containing the plurality of ions in the main surface of the sample, and a control section configured to control a position of the sample or a spatial distribution of electrons emitted from the filament so that a direction of eccentricity of a center of gravity of the ion beam coincides with a direction of a normal line of the main surface.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 26, 2006
    Inventors: Hiroshi Itokawa, Yoshimasa Kawase, Kyoichi Suguro
  • Publication number: 20040196464
    Abstract: An apparatus for evaluating semiconductor material having a pump laser configured to irradiate a pump beam modulated at a modulation frequency on a semiconductor wafer, a probe laser configured to irradiate a probe beam on the semiconductor wafer, and a detector configured to detect a reflection of the probe beam from the semiconductor wafer.
    Type: Application
    Filed: August 7, 2003
    Publication date: October 7, 2004
    Inventors: Haruko Akutsu, Katsumi Rikimaru, Kyoichi Suguro, Tatsuya Shima, Yoshimasa Kawase, Atsushi Murakoshi
  • Patent number: 6769908
    Abstract: A wafer heat-treatment system for processing a wafer by a high-temperature heat-treatment process and cooling the heat-treated wafer, comprises walls surrounding a closed space placing the wafer and having a hollow sealing a gas therein, and a pressure-regulating unit connecting to the hollow for regulating pressure in the hollow. Hence, the wafer heat-treatment system reduces power consumption by heating lamps by carrying out an evacuating process before the high-temperature heat-treatment process, and shortens the time necessary for the cool down process by a pressurizing process that is carried out after the completion of the high-temperature heat-treatment process.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Yoshimasa Kawase
  • Publication number: 20020148135
    Abstract: A wafer heat-treatment system for processing a wafer by a high-temperature heat-treatment process and cooling the heat-treated wafer, comprises walls surrounding a closed space placing the wafer and having a hollow sealing a gas therein, and a pressure-regulating unit connecting to the hollow for regulating pressure in the hollow. Hence, the wafer heat-treatment system reduces power consumption by heating lamps by carrying out an evacuating process before the high-temperature heat-treatment process, and shortens the time necessary for the cool down process by a pressurizing process that is carried out after the completion of the high-temperature heat-treatment process.
    Type: Application
    Filed: February 6, 2002
    Publication date: October 17, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Yoshimasa Kawase