Patents by Inventor Yoshimasa Mikajiri
Yoshimasa Mikajiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110031550Abstract: A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.Type: ApplicationFiled: March 19, 2010Publication date: February 10, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Komori, Hideaki Aochi, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20110018052Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.Type: ApplicationFiled: June 22, 2010Publication date: January 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Fujiwara, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20110018050Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.Type: ApplicationFiled: March 19, 2010Publication date: January 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko FUJIWARA, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20110013454Abstract: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.Type: ApplicationFiled: March 18, 2010Publication date: January 20, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Tomoo Hishida, Yoshihisa Iwata, Megumi Ishiduki, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhel Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20110002172Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.Type: ApplicationFiled: March 22, 2010Publication date: January 6, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KITO, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20100327340Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.Type: ApplicationFiled: June 23, 2010Publication date: December 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeto OOTA, Yoshimasa Mikajiri, Masaru Kito, Ryouhei Kirisawa
-
Publication number: 20100327339Abstract: A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductiType: ApplicationFiled: March 22, 2010Publication date: December 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu TANAKA, Ryota Katsumata, Hideaki Aochi, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
-
Publication number: 20100320526Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor.Type: ApplicationFiled: March 19, 2010Publication date: December 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KIDOH, Ryota KATSUMATA, Masaru KITO, Yoshiaki FUKUZUMI, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Tomoko FUJIWARA, Yoshimasa MIKAJIRI, Shigeto OOTA, Hideaki AOCHI, Ryouhei KIRISAWA, Junya MATSUNAMI
-
Publication number: 20100301405Abstract: A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.Type: ApplicationFiled: March 19, 2010Publication date: December 2, 2010Inventors: Shigeto OOTA, Yoshimasa Mikajiri, Ryouhei Kirisawa
-
Publication number: 20100244119Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: March 16, 2010Publication date: September 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota