Abstract: A timing signal generator receives a plurality of control signals in synchronization with a clock signal, and generates a timing signal according to a combination of the control signals. A delay circuit delays an input signal received asynchronously to the clock signal by a predetermined time. A receiving circuit receives the input signal which is delayed by the delay circuit, in synchronization not with the clock signal but with the timing signal. Namely, the receiving circuit operates asynchronously to the clock signal, and receives only necessary input signals for the semiconductor integrated circuit. This lowers operation frequency of the receiving circuit, thereby reducing power consumption. The number of the circuits to be operated in synchronization with the clock signal can be reduced, by which reduces standby current. An increase in the standby current is gradual even when frequency of the clock signal goes high.

Abstract: A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block.

Abstract: A semiconductor memory device that reduces the probability of the penalties of wirings arising. An address input circuit receives an address signal input. A drive circuit drives a memory array in compliance with the address signal. A signal line connects the address input circuit and the drive circuit. A redundant circuit is located near the drive circuit and substitutes other lines including a redundant line for a defective line in the memory array. A defective line information store circuit stores information showing the defective line. A supply circuit supplies information stored in the defective line information store circuit to the redundant circuit via the signal line. This structure enables to transmit an address signal and information regarding a defective line by a common signal line and to reduce the number of wirings and the probability of the penalties of wirings arising.

Abstract: The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality of reference currents. The current comparing units in the receiver respectively compares reference currents with output current from the transmitter and restores the logic values. That is, the current is varied in correspondence with the logic values that are transmitted from the transmitter to the receiver, wherein the logic values are restored in the receiver according to a difference in the current value. Forming a plurality of current comparing units in the receiver makes it possible to easily compare the values of the output current from the transmitter and a plurality of reference currents. Therefore, the number of multi-valued bits can be easily increased so as to construct a high bit-rate multi-valued input/output interface.

Abstract: The command decoder decodes a command signal to generate a command control signal. The mask circuit receives the command control signal to recognize the operating state of the memory core thereafter, and activates a mask signal when the command signal to be supplied anew is unacceptable. The control circuit disables an operation of the memory core corresponding to the command control signal when the mask signal is activated. Illegal commands are decided by the mask circuit alone. On this account, the control circuit need not be provided with a circuit for individually determining commands as illegal in accordance with actual operating states. Therefore, using the mask circuit makes it possible to prevent malfunctions resulting from illegal commands with facility and reliability. The intrinsic functions of the control circuit have only to be verified at the time of design and circuit modifications, which results in improving design efficiency.

Abstract: The supply connecting circuit selects one input signal from a plurality of input signals corresponding to a plurality of select signals in response to the activation of any one of the select signals. The supply connecting circuit connects a supply to either of the inverting circuits in the latch depending on the input signal selected. The latch is forced to be unbalanced due to the activation of one inverting circuit so as to latch a value corresponding to the input signal selected by the select signal. A value to be latched is determined with the states of the input signals supplied at the activation of a select signal. This minimizes the settling periods of the input signals with respect to the select signals. As a result, the timing margins of the circuit increase, thereby realizing high speed operations.

Abstract: The semiconductor integrated circuit according to the present invention comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receiving circuits are made equal in propagation delay times from their respective input terminals to the receiving circuit. Since the receiving circuits can receive the input signals of little skew, the timing margin required for the reception is minimized. That is, high speed operation becomes possible. At the same time, because the input signals corresponding to each individual receiving circuit are made equal in propagation delay time, the wiring for transmitting the input signals can be arranged in a minimum area. This can reduce the chip area, with reduction in chip costs.

Abstract: The command decoder decodes a command signal to generate a command control signal. The mask circuit receives the command control signal to recognize the operating state of the memory core thereafter, and activates a mask signal when the command signal to be supplied anew is unacceptable. The control circuit disables an operation of the memory core corresponding to the command control signal when the mask signal is activated. Illegal commands are decided by the mask circuit alone. On this account, the control circuit need not be provided with a circuit for individually determining commands as illegal in accordance with actual operating states. Therefore, using the mask circuit makes it possible to prevent malfunctions resulting from illegal commands with facility and reliability. The intrinsic functions of the control circuit have only to be verified at the time of design and circuit modifications, which results in improving design efficiency.

Abstract: The supply connecting circuit selects one input signal from a plurality of input signals corresponding to a plurality of select signals in response to the activation of any one of the select signals. The supply connecting circuit connects a supply to either of the inverting circuits in the latch depending on the input signal selected. The latch is forced to be unbalanced due to the activation of one inverting circuit so as to latch a value corresponding to the input signal selected by the select signal. A value to be latched is determined with the states of the input signals supplied at the activation of a select signal. This minimizes the settling periods of the input signals with respect to the select signals. As a result, the timing margins of the circuit increase, thereby realizing high speed operations.

Abstract: A novel semiconductor device having two different power circuits is disclosed. Even if the output of the stage before a voltage conversion circuit declines due to the decline of the level of the power circuits or the voltage drop through a resistor, the voltage conversion circuit performs a normal operation. The semiconductor device comprises a first power circuit for generating a first source voltage, a second power circuit for generating a second source voltage higher than the first source voltage, and a second power level detection circuit for detecting the second source voltage. The first power circuit changes the first source voltage in accordance with the result of detection by the second power level detection circuit.

Abstract: A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage.