Patents by Inventor Yoshimi Egawa

Yoshimi Egawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020119599
    Abstract: A first adhesive tape is attached to a first major surface of a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor chip regions. Protrusion electrodes are formed on a second major surface of the semiconductor wafer within the plurality of semiconductor chip regions. Portions of the semiconductor wafer located between the plurality of chip regions are removed to form a plurality of semiconductor chip. Intervals between the semiconductor chips are then expanded. Respective first major surfaces of the wiring substrates are coupled to the corresponding second major surfaces of the semiconductor chips by the protrusion electrodes to form preliminarily structures each of which is comprised of the semiconductor chip and the wiring substrate. A second adhesive tape is attached to second major surfaces of the wiring substrates. The first adhesive tape from the semiconductor chips.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 29, 2002
    Inventors: Yoshimi Egawa, Kazumi Shinchi, Takeshi Niigaki
  • Patent number: 6426554
    Abstract: A semiconductor device includes a semiconductor chip having a mounting surface with connecting pads mounted thereon, and a film having a gluing surface facing the mounting surface of the chip and a mounting surface for mounting a circuit board on a surface opposite the gluing surface. The circuit board has connecting pads mounted thereon. On the mounting surface of the film, a wiring pattern is formed with connecting terminals connected to the connecting pads of the circuit board. The film is an anisotropically conductive film and exhibits conductivity at local areas when subjected to pressure between the wiring pattern and the connecting pads of the semiconductor chip. The gluing surface of the film is attached solidly to the semiconductor chip, wherein the film maintains conductivity in view of a cooling process after heating.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: July 30, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshimi Egawa
  • Patent number: 6376278
    Abstract: A first adhesive tape is attached to a first major surface of a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor chip regions. Protrusion electrodes are formed on a second major surface of the semiconductor wafer within the plurality of semiconductor chip regions. Portions of the semiconductor wafer located between the plurality of chip regions are removed to form a plurality of semiconductor chips. Intervals between the semiconductor chips are then expanded. Respective first major surfaces of the wiring substrates are coupled to the corresponding second major surfaces of the semiconductor chips by the protrusion electrodes to form preliminarily structures each of which is comprised of the semiconductor chip and the wiring substrate. A second adhesive tape is attached to second major surfaces of the wiring substrates. The first adhesive tape is removed from the semiconductor chips.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: April 23, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshimi Egawa, Kazumi Shinchi, Takeshi Niigaki
  • Patent number: 6259163
    Abstract: A metal pattern 4 is formed at a rear surface of a substrate 3 at a front surface of which a molded semiconductor chip is mounted, the metal pattern 4 is covered with an insulating film 5 except at its connecting area 4a and a solder ball 6 is bonded to the connecting area 4a. The area of the metal pattern 4 other than the connecting area 4a inclines toward the substrate 3 and gradually becomes thinner toward the outside. Stress, which is applied to the solder ball 6, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks X is reduced and the solder ball which is used to achieve connection with an external substrate is effectively prevented from becoming electrically disconnected.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: July 10, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa, Noritaka Anzai
  • Patent number: 6251704
    Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: June 26, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa, Noritaka Anzai
  • Patent number: 6229215
    Abstract: In a semiconductor device 1 having a first semiconductor chip 11 mounted at a front surface of a substrate 10 and a plurality of bumps 15 formed at a rear surface of the substrate 10, a second semiconductor chip 17 is mounted at an area 16 formed at the center of the rear surface of the substrate 10 where the bumps 15 are not present.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: May 8, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshimi Egawa
  • Patent number: 6204563
    Abstract: A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: March 20, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai, Yoshimi Egawa
  • Patent number: 6130480
    Abstract: Described herein are a structure and a method for packaging a semiconductor chip. The structure comprises a semiconductor chip having a plurality of bumps formed thereon, a substrate having copper-made wiring patterns with the bumps joined thereto, which are formed so as to correspond to forming positions of the bumps, and a polyimide tape having adhesive layers provided on both surfaces for joining the semiconductor chip and the substrate to one another upon positioning. A spacing defined between the semiconductor chip and the substrate is sealed with a resin layer. A material for the substrate is selected so that a thermal expansion coefficient of the substrate is substantially equal to that of the polyimide tape.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 10, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa
  • Patent number: 5994168
    Abstract: A method of manufacturing a semiconductor device which allows reliability of connection to be improved and manufacturing time to be reduced includes sandwiching a sheet-shaped unhardended hardenable material between a semiconductor chip and an interposer or substrate. The hardenable material is then melted, thereby bonding the semiconductor chip and the interposer, the surface of the semiconductor chip opposite the interposer being covered with the hardening resin. The hardenable material is then hardened in an appropriate manner.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: November 30, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshimi Egawa
  • Patent number: 5863815
    Abstract: A method of manufacturing a semiconductor device which allows reliability of connection to be improved and manufacturing time to be reduced includes sandwiching a sheet-shaped unhardended hardenable material between a semiconductor chip and an interposer or substrate. The hardenable material is then melted, thereby sealing the semiconductor chip and the interposer, including along connection terminals therebetween. The hardenable material is then hardened in an appropriate manner.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: January 26, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshimi Egawa