Abstract: A redundant control system in which three output signals from three equivalent signal processors are compared with each other to judge whether each of the output signals is normal or abnormal, an abnormal output signal thus determined is replaced by a set signal having a predetermined level, and then a majority operation is performed for normal output signals and the set signal to obtain a control signal. The control signal is formed of the logical product or logical sum of two normal output signals according as the predetermined level of the set signal is "1" or "0". In the case where a circuit for generating the above-mentioned control signal are formed in triplicate and a majority operation is performed for three control signals, a fault occurring at other circuit portions than a majority logic circuit at the final stage is permissible.